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  one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 rev. prf 10/02 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. active and apparent energy metering ic with di/dt sensor interface ade7753* features high accuracy, supports iec 61036 and iec61268 on-chip digital integrator enables direct interface with current sensors with di/dt output the ade7753 supplies active, reactive and apparent energy, sampled waveform, current and voltage rms less than 0.1% error over a dynamic range of 1000 to 1 positive only energy accumulation mode available an on-chip user programmable threshold for line voltage surge and sag, and psu supervisory digital power, phase & input offset calibration an on-chip temperature sensor (3c typical) a spi compatible serial interface a pulse output with programmable frequency an interrupt request pin (irq) and status register proprietary adcs and dsp provide high accuracy data over large variations in environmental conditions and time reference 2.4v8% (20 ppm/c typical) with external overdrive capability single 5v supply, low power (25mw typical) functional block diagram *u.s. patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending. precise phase matching between the current and voltage channels. the integrator can be switched on and off based on the current sensor selected. the ade7753 contains an active energy register. it is capable of holding more than 200 seconds of accumulated power at full load. data is read from the ade7753 via the serial interface. the ade7753 also provides a pulse output (cf) with output frequency is proportional to the active power. in addition to rms calculation and active and apparent power information, the ade7753 also accumulates the signed reactive energy. the ade7753 also provides various system calibration features, i.e., channel offset correction, phase calibration and power calibration. the part also incorporates a detection circuit for short duration low or high voltage variations. the ade7753 has a positive only accumulation mode which gives the option to accumulate energy only when positive power is detected. an internal no-load threshold ensures that the part does not exhibit any creep when there is no load. a zero crossing output (zx) produces an output which is synchronized to the zero crossing point of the line voltage. this information is used in the ade7753 to measure the line's period. the signal is also used internally to the chip in the line cycle active and apparent energy accumulation mode. this enables a faster and more precise energy accumu- lation and is useful during calibration. this signal is also useful for synchronization of relay switching with a voltage zero crossing. the interrupt request output is an open drain, active low logic output. the interrupt status register indicates the nature of the interrupt, and the interrupt enable register controls which event produces an output on the irq pin. the ade7753 is available in 20-lead ssop package.   dvdd hpf lpf2 dgnd clkout v1p v1n + - + - v2p v2n 2.4v reference adc avdd pga clkin ref in/out cf reset agnd 4k ? phcal[5:0] multiplier apos[15:0] din dout sclk cs sag zx irq ade7753 registers & serial interface ade7753 temp sensor lpf1 integrator  dt vrmsos[11:0] irmsos[11:0] wgain[11:0] wdiv[7:0] cfnum[11:0] cfden[11:0] dfc vagain[11:0] vadiv[7:0]   pga adc preliminary technical data preliminary technical data general description the ade7753 is an accurate active and apparent energy measurements ic with a serial interface and a pulse output. the ade7753 incorporates two second order sigma delta adcs, a digital integrator (on ch1), reference circuitry, temperature sensor, and all the signal processing required to perform rms calculation on the voltage and current, active, reactive, and apparent energy measurement. an on-chip digital integrator provides direct interface to di/ dt current sensors such as rogowski coils. the digital integrator eliminates the need for external analog integrator, and this solution provides excellent long-term stability and a
-2- (av dd = dv dd = 5v 5%, agnd = dgnd = 0v, on-chip reference, clkin = 3.579545mhz xtal, tmin to tmax = -40c to +85c) rev. prf 10/02 preliminary technical data ade7753?specifications 1,3 parameter spec units test conditions/comments energy measurement accuracy measurement bandwidth 14 k h z clkin = 3.579545 mhz measurement error 1 on channel 1 channel 2 = 300mv rms/60hz, gain = 2 channel 1 range = 0.5v full-scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.1 % typ over a dynamic range 1000 to 1 gain = 8 0.1 % typ over a dynamic range 1000 to 1 gain = 16 0.2 % typ over a dynamic range 1000 to 1 channel 1 range = 0.25v full-scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.1 % typ over a dynamic range 1000 to 1 gain = 8 0.2 % typ over a dynamic range 1000 to 1 gain = 16 0.2 % typ over a dynamic range 1000 to 1 channel 1 range = 0.125v full-scale gain = 1 0.1 % typ over a dynamic range 1000 to 1 gain = 2 0.1 % typ over a dynamic range 1000 to 1 gain = 4 0.2 % typ over a dynamic range 1000 to 1 gain = 8 0.2 % typ over a dynamic range 1000 to 1 gain = 16 0.4 % typ over a dynamic range 1000 to 1 phase error 1 between channels 0.05 max line frequency = 45hz to 65hz, hpf on ac power supply rejection 1 av dd = dv dd = 5v+175mv rms/ 120hz output frequency variation (cf) 0.2 % typ channel 1 = 20mv rms, gain = 16, range = 0.5v channel 2 = 300mv rms/60hz, gain = 1 dc power supply rejection 1 av dd = dv dd = 5v 250mv dc output frequency variation (cf) 0.3 % typ channel 1 = 20mv rms/60hz, gain = 16, range = 0.5v channel 2 = 300mv rms/60hz, gain = 1 analog inputs see analog inputs section maximum signal levels 0.5 v max v1p, v1n, v2n and v2p to agnd input impedance (dc) 390 k ? 1 = 1 = 1 1 1 = 0 1 = 0 = 0 1 = 0 = 01 1 = 01 = 0 1 1 = 0 0 = 1 1 = 0 0 = 1 1 = 01 0 = 1 1 0 = 1 1 1 1 10 1 = 0 10 = 0 1 1 = 1 see channel 1 sampling signal-to-noise plus distortion 62 db typ 150mv rms/60hz, range = 0.5v, gain = 2 bandwidth (-3db) 14 khz clkin = 3.579545mhz channel 2 see channel 2 sampling signal-to-noise plus distortion 52 db typ 150mv rms/60hz, gain = 2 bandwidth (-3db) 140 hz clkin = 3.579545mhz
ade7753 ?3? rev. prf 10/02 preliminary technical data parameter spec units test conditions/comments reference input ref in/out input voltage range 2.6 v max 2.4 v +8% 2.2 v min 2.4v -8% input capacitance 10 pf max on-chip reference n ominal 2.4v at ref in/out pin reference error 200 mv max current source 10 a max output impedance 4 k  min temperature coefficient 20 ppm/c typ clkin n ote all specifications clkin of 3.579545mhz input clock frequency 4 mhz max 1 mhz min logic inputs reset , din, sclk, clkin and cs input high voltage, v inh 2.4 v min dv dd = 5 v 10% input low voltage, v inl 0.8 v max dv dd = 5 v 10% input current, i in 3 a max typically 10na, v in = 0v to dv dd input capacitance, c in 10 pf max logic outputs 3 sag & irq open drain outputs, 10k  pull up resistor output high voltage, v oh 4 v min i source = 5ma output low voltage, v ol 0.4 v max i sink = 0.8ma zx & dout output high voltage, v oh 4 v min i source = 5ma output low voltage, v ol 0.4 v max i sink = 0.8ma cf output high voltage, v oh 4 v min i source = 5ma output low voltage, v ol 1 v max i sink = 7ma power supply for specified performance av dd 4.75 v min 5v - 5% 5.25 v max 5v +5% dv dd 4.75 v min 5v - 5% 5.25 v max 5v + 5% ai dd 3 ma max typically 2.0 ma di dd 4 ma max typically 3.0 ma notes: 1 see terminology section for explanation of specifications 2 see plots in typical performance graphs 3 specifications subject to change without notice 4 see analog inputs section 200 a 1.6 ma i oh i ol c l 50pf to output pin +2.1v load circuit for timing specifications ordering guide model package option* ADE7753ARS rs-20 ADE7753ARSrl rs-20 eval-ade7753eb ade7753 evaluation board * rs = shrink small outline package in tubes; rsrl = shrink small outline package in reel.
ade7753 ?4? rev. prf 10/02 preliminary technical data cs sclk din a4 a3 a2 a1 a0 db7 most significant byte t 1 t 2 t 3 t 4 t 5 t 8 1 db0 db7 db0 t 6 least significant byte t 7 t 7 00 command byte cs sclk din a4 a3 a2 a1 a0 t 1 t 11 t 11 t 9 db7 dout t 12 db0 db0 db7 t 10 t 13 most significant byte least significant byte 000 command byte serial write timing serial read timing ade7753 timing characteristics 1,2 parameter a,b versions units test conditions/comments write timing t 1 20 ns (min) cs falling edge to first sclk falling edge t 2 150 ns (min) sclk logic high pulse width t 3 150 ns (min) sclk logic low pulse width t 4 10 ns (min) v alid data set up time before falling edge of sclk t 5 5 ns (min) data hold time after sclk falling edge t 6 t b d ns (min) minimum time between the end of data byte transfers. t 7 t b d ns (min) minimum time between byte transfers during a serial write. t 8 100 ns (min) cs hold time after sclk falling edge. read timing t 9 3.1 us (min) minimum tim e between read command (i.e. a write to communication reigster) and data read. t 10 t b d ns (min) minimum time between data byte transfers during a multibyte read. t 11 3 30 ns (min) data access time after sclk rising edge following a write to the communications register t 12 4 100 ns (max) bus relinquish time after falling edge of sclk. 10 ns (min) t 13 4 100 ns (max) bus relinquish time after rising edge of cs . 10 ns (min) notes 1 sample tested during initial release and after any redesign or process change that may affect this parameter. all input signals are specified with tr = tf = 5ns (10% to 90%) and timed from a voltage level of 1.6v. 2 see timing diagram below and serial interface section of this data sheet. 3 measured with the load circuit in figure 1 and defined as the time required for the output to cross 0.8v or 2.4v. 4 derived from the measured time taken by the data outputs to change 0.5v when loaded with the circuit in figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50pf capacitor. this means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. (av dd = dv dd = 5v 5%, agnd = dgnd = 0v, on-chip reference, clkin = 3.579545mhz xtal, tmin to tmax = -40c to +85c)
ade7753 ?5? rev. prf 10/02 preliminary technical data terminology measurement error the error associated with the energy measurement made by the ade7753 is defined by the following formula: % energy true energy true ade by registered energy erro r percentage 100 7753 ? ? ? ? ? ? ? ? ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumu- late on the human body and test equipment and can discharge without detection. although the ade7753 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. input signal levels when the supplies are varied 5%. any error introduced is again expressed as a percentage of reading. adc offset error this refers to the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd the adcs still see a dc analog input signal. the magnitude of the offset depends on the gain and input range selection - see characteristic curves. however, when hpf1 is switched on the offset is removed from channel 1 (current) and the power calculation is not affected by this offset. the offsets may be removed by performing an offset calibration - see analog inputs . gain error the gain error in the ade7753 adcs is defined as the difference between the measured adc output code (minus the offset) and the ideal output code - see channel 1 adc & channel 2 adc. it is measured for each of the input ranges on channel 1 (0.5v, 0.25v and 0.125v). the difference is expressed as a percentage of the ideal code. gain error match the gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 (for each of the input ranges) and a gain of 2, 4, 8, or 16. it is expressed as a percentage of the output adc code obtained under a gain of 1. this gives the gain error observed when the gain selection is changed from 1 to 2, 4, 8 or 16. warning! esd sensitive device
ade7753 ?6? rev. prf 10/02 preliminary technical data pin function description pin no. mnemonic description 1 reset reset pin for the ade7753. a logic low on this pin will hold the adcs and digital circuitry (including the serial interface) in a reset condition. 2dv dd digital power supply. this pin provides the supply voltage for the digital circuitry in the ade7753. the supply voltage should be maintained at 5v 5% for specified op- eration. this pin should be decoupled to dgnd with a 10f capacitor in parallel with a ceramic 100nf capacitor. 3av dd analog power supply. this pin provides the supply voltage for the analog circuitry in the ade7753. the supply should be maintained at 5v 5% for specified operation. every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. the typical performance graphs in this data sheet show the power supply rejection performance. this pin should be decoupled to agnd with a 10f capacitor in parallel with a ceramic 100nf capacitor. 4,5 v1p, v1n analog inputs for channel 1. this channel is intended for use with the di/dt current transducer such as rogowski coil or other current sensor such as shunt or current trans- former (ct). these inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5v, 0.25v and 0.125v, depending on the full scale selection - see analog inputs . channel 1 also has a pga with gain selections of 1, 2, 4, 8 or 16. the maximum signal level at these pins with respect to agnd is 0.5v. both inputs have internal esd protection circuitry and in addition an overvoltage of 6v can be sustained on these inputs without risk of permanent damage. 6,7 v2n, v2p analog inputs for channel 2. this channel is intended for use with the voltage trans- ducer. these inputs are fully differential voltage inputs with a maximum differential signal level of 0.5v. channel 2 also has a pga with gain selections of 1, 2, 4, 8 or 16. the maximum signal level at these pins with respect to agnd is 0.5v. both inputs have internal esd protection circuitry, and an overvoltage of 6v can be sus- tained on these inputs without risk of permanent damage. 8 agnd this pin provides the ground reference for the analog circuitry in the ade7753, i.e. adcs and reference. this pin should be tied to the analog ground plane or the quietest ground reference in the system. this quiet ground reference should be used for all ana- log circuitry, e.g. anti-aliasing filters, current and voltage transducers etc. in order to keep ground noise around the ade7753 to a minimum, the quiet ground plane should only connected to the digital ground plane at one point. it is acceptable to place the entire device on the analog ground plane - see applications information . 9 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 2.4v 8% and a typical temperature coefficient of 20ppm/c. an external reference source may also be connected at this pin. in either case this pin should be decoupled to agnd with a 1f ceramic capacitor. 10 dgnd this provides the ground reference for the digital circuitry in the ade7753, i.e. multi- plier, filters and digital-to-frequency converter. because the digital return currents in the ade7753 are small, it is acceptable to connect this pin to the analog ground plane of the system - see applications information . however, high bus capacitance on the dout pin may result in noisy digital current which could affect performance. 11 c f calibration frequency logic output. the cf logic output gives active power informa- tion. this output is intended to be used for operational and calibration purposes. the full-scale output frequency can be adjusted by writing to the cfden and cfnum register?see energy to frequency conversion. 12 z x voltage waveform (channel 2) zero crossing output. this output toggles logic high and low at the zero crossing of the differential signal on channel 2?see zero crossing detection . 13 sag this open drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (channel 2) is crossed for a specified duration. see line volt- age sag detection. 14 irq interrupt request output. this is an active low open drain logic output. maskable interrupts include: active energy register roll-over, active energy register at half level, and arrivals of new waveform samples. see ade7753 interrupts .
ade7753 ?7? rev. prf 10/02 preliminary technical data pin configuration ssop packages 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 dgnd cs clkou t clkin zx cf ade7753 top view (not to scale) agnd irq reset dvdd v1p v1n v2n v2p sag ref in/out 11 12 avdd din dout sclk pin no. mnem onic description 15 clkin master clock for adcs and digital signal processing. an external clock can be pro- vided at this logic input. alternatively, a parallel resonant at crystal can be connected across clkin and clkout to provide a clock source for the ade7753. the clock frequency for specified operation is 3.579545mhz. ceramic load capacitors of between 22pf and 33pf should be used with the gate oscillator circuit. refer to crystal manu- facturers data sheet for load capacitance requirements. 16 clkout a crystal can be connected across this pin and clkin as described above to provide a clock source for the ade7753. the clkout pin can drive one cmos load when either an external clock is supplied at clkin or a crystal is being used. 17 cs chip select. part of the four wire spi serial interface. this active low logic input al- lows the ade7753 to share the serial bus with several other devices. see ade7753 serial interface . 18 sclk serial clock input for the synchronous serial interface. all serial data transfers are synchronized to this clock?see ade7753 serial interface . the sclk has a schmitt-trigger input for use with a clock source which has a slow edge transition time, e.g., opto- isolator outputs. 19 dout d ata output for the serial interface. data is shifted out at this pin on the rising edge of sclk. this logic output is normally in a high impedance state unless it is driving data onto the serial data bus?see ade7753 serial interface .. 20 d i n data input for the serial interface. data is shifted in at this pin on the falling edge of sclk?see ade7753 serial interface ..
ade7753 ?8? rev. prf 10/02 preliminary technical data typical performance characteristics-ade7753 tbd tpc 1? error as a % of reading (gain=1) tbd tpc 2? error as a % of reading (gain=4) tbd tpc 3? error as a % of reading (gain=16) tbd tpc 4? error as a % of reading (full-scale input for chan- nel 1=0.25v, gain=4) tbd tpc 5? error as a % of reading (full-scale input for chan- nel 1=0.125v, gain=8) tbd tpc 6? test circuits for performance curves
ade7753 ?9? rev. prf 10/02 preliminary technical data analog inputs the ade7753 has two fully differential voltage input chan- nels. the maximum differential input voltage for input pairs v1p/v1n and v2p/v2n are 0.5v. in addition, the maxi- mum signal level on analog inputs for v1p/v1n and v2p/ v2n are 0.5v with respect to agnd. each analog input channel has a pga (programmable gain amplifier) with possible gain selections of 1, 2, 4, 8 and 16. the gain selections are made by writing to the gain regis- ter?see figure 2. bits 0 to 2 select the gain for the pga in channel 1 and the gain selection for the pga in channel 2 is made via bits 5 to 7. figure 1 shows how a gain selection for channel 1 is made using the gain register. v1p v1n v in k.v in + -  + gain[7:0] gain (k) selection offset adjust (50mv) ch1os[7:0] bit 0 to 5: sign magnitude coded offset correction bit 6: not used bit 7: digital integrator (on=1, off=0; default on) figure 1? pga in channel 1 in addition to the pga, channel 1 also has a full scale input range selection for the adc. the adc analog input range selection is also made using the gain register?see figure 2. as mentioned previously the maximum differential input voltage is 1v. however, by using bits 3 and 4 in the gain register, the maximum adc input voltage can be set to 0.5v, 0.25v or 0.125v. this is achieved by adjusting the adc reference?see ade7753 reference circuit . table i below sum- marizes the maximum differential input signal level on channel 1 for the various adc range and gain selections. gain register* channel 1 and channel 2 pga control addr: 0fh 0 1 2 3 4 5 6 7 pga 2 gain select 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16 00 0 0 0 0 0 0 *register contents show power on defaults pga 1 gain select 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16 channel 1 full scale select 00 = 0.5v 01 = 0.25v 10 = 0.125v figure 2? ade7753 analog gain register it is also possible to adjust offset errors on channel 1 and channel 2 by writing to the offset correction registers (ch1os and ch2os respectively). these registers allow channel offsets in the range 20mv to 50mv (depending on the gain setting) to be removed. note that it is not necessary to perform an offset correction in an energy measurement application if hpf in channel 1 is switched on. figure 3 shows the effect of offsets on the real power calculation. as can be seen from figure 3, an offset on channel 1 and channel 2 will contribute a dc component after multiplica- tion. since this dc component is extracted by lpf2 to generate the active (real) power information, the offsets will have contributed an error to the active power calculation. this problem is easily avoided by enabling hpf in channel 1. by removing the offset from at least one channel, no error component is generated at dc by the multiplication. error terms at cos(w.t) are removed by lpf2 and by integration of the active power signal in the active energy register (aen- ergy[23:0]) ? see energy calculation . v.i 2 frequency (rad/s)  2  0 v os .i os v os .i i os .v dc component (including error term) is extracted by the lpf for real power calculation figure 3? effect of channel offsets on the real power cal- culation the contents of the offset correction registers are 6-bit, sign and magnitude coded. the weighting of the lsb size depends on the gain setting, i.e., 1, 2, 4, 8 or 16. table ii below shows the correctable offset span for each of the gain settings and the lsb weight (mv) for the offset correction registers. the maximum value which can be written to the offset correction registers is 31 decimal ?see figure 4. figure 4 shows the relationship between the offset correc- tion register contents and the offset (mv) on the analog inputs for a gain setting of one. in order to perform an offset adjustment, the analog inputs should be first connected to agnd, and there should be no signal on either channel 1 or channel 2. a read from channel 1 or channel 2 using the max signal adc input range selection channel 1 0.5v 0.25v 0.125v 0.5v g ain = 1 ? ? 0.25v g ain = 2 gain = 1 ? 0.125v g ain = 4 gain = 2 gain = 1 0.0625v g ain = 8 gain = 4 gain = 2 0.0313v gain = 16 gain = 8 gain = 4 0.0156v ? gain = 16 gain = 8 0.00781v ? ? gain = 16 table i maximum input signal levels for channel 1
ade7753 ?10? rev. prf 10/02 preliminary technical data waveform register will give an indication of the offset in the channel. this offset can be canceled by writing an equal and opposite offset value to the relevant offset register. the offset correction can be confirmed by performing another read. note when adjusting the offset of channel 1, one should disable the digital integrator and the hpf. ch1os[5:0] 00h 1fh 3fh +50mv -50mv 0mv offset adjust 01, 1111b 11, 1111b sign + 5 bits sign + 5 bits figure 4? channel offset correction range (gain = 1) gain correctable span lsb size 1 50mv 1.61mv/lsb 2 37mv 1.19mv/lsb 4 30mv 0.97mv/lsb 8 26mv 0.84mv/lsb 16 24mv 0.77mv/lsb table ii offset correction range di/dt current sensor and digital integrator di/dt sensor detects changes in magetic field caused by ac current. figure 5 shows the principle of a di/dt current sensor. + - emf (electromotive force) induced by changes in magnetic flux density (d/d t) magnetic field created by current (directly proportional to current) figure 5? principle of a di/dt current sensor the flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. the changes in the magnetic flux density passing through a conductor loop generates an electromotive force (emf) between the two ends of the loop. the emf is a voltage signal which is proportional to the di/dt of the current. the voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. the current signal needs to be recovered from the di/dt signal before it can be used. an integrator is therefore necessary to restore the signal to its original form. the ade7753 has a built-in digital integrator to recover the current signal from the di/dt sensor. the digital integrator on channel 1 is switched off by default when the ade7753 is powered up. setting the msb of ch1os register will turn on the integrator. figures 6 to 9 show the magnitude and phase response of the digital integrator. 10 2 10 3 -50 -40 -30 -20 -10 0 10 frequency-hz gain-db figure 6? combined gain response of the digital integrator and phase compensator 10 2 10 3 -90.5 -90 -89.5 -89 -88.5 -88 frequency-hz phase-degrees figure 7? combined phase response of the digital integra- tor and phase compensator 40 45 50 55 60 65 70 -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 frequency-hz gain-db figure 8? combined gain response of the digital integrator and phase compensator (40hz to 70hz)
ade7753 ?11? rev. prf 10/02 preliminary technical data zero crossing detection the ade7753 has a zero crossing detection circuit on channel 2. this zero crossing is used to produce an external zero cross signal (zx) and it is also used in the calibration mode - see energy calibration . the zero crossing signal is also used to initiate a temperature measurement on the ade7753 - see temperature measurement . figure 10 shows how the zero cross signal is generated from the output of lpf1. v2p v2n adc 2 pga2 1 x1, x2, x4, x8, x16 reference gain[7:5] v2 to multiplier -63% to + 63% fs lpf1 f -3db = 140hz zero cross zx v2 lpf1 zx 23.2 8 @ 60hz 0.92 1.0 figure 10? zero cross detection on channel 2 the zx signal will go logic high on a positive going zero crossing and logic low on a negative going zero crossing on channel 2. the zero crossing signal zx is generated from the output of lpf1. lpf1 has a single pole at 156hz (at clkin = 3.579545mhz). as a result there will be a phase lag between the analog input signal v2 and the output of lpf1. the phase response of this filter is shown in the channel 2 sampling section of this data sheet. the phase lag response of lpf1 results in a time delay of approximately 0.97ms (@ 60hz) between the zero crossing on the analog inputs of channel 2 and the rising or falling edge of zx. the zero-crossing detection also drives one flag bit in the interrupt status register. an active low in the irq output will also appear if the corresponding bit in the interrupt enable register is set to logic one. the flag in the interrupt status register as well as the irq output are reset to their default value when the interrupt status register with reset (rststatus) is read. zero crossing timeout the zero crossing detection also has an associated time-out register zxtout. this unsigned, 12-bit register is decremented (1 lsb) every 128/clkin seconds. the reg- ister is reset to its user programmed full scale value every time a zero crossing on channel 2 is detected. the default power on value in this register is fffh. if the register decrements to zero before a zero crossing is detected and the dissag bit in the mode register is logic zero, the sag irq i i is ai si is i i riasr a s i 40 45 50 55 60 65 70 -90.05 -90 -89.95 -89.9 -89.85 -89.8 -89.75 -89.7 frequency-hz phase-degrees figure 9? combined phase response of the digital integra- tor and phase compensator (40hz to 70hz) note that the integrator has a -20db/dec attenuation and approximately -90 phase shift. when combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. however, the di/dt sensor has a 20db/dec gain associated with it, and generates significant high frequency noise, a more effective anti-aliasing filter is needed to avoid noise due to aliasing? see antialias filter . when the digital integrator is switched off, the ade7753 can be used directly with a conventional current sensor such as current transformer (ct) or a low resistance current shunt.
ade7753 ?12? rev. prf 10/02 preliminary technical data power supply monitor the ade7753 also contains an on-chip power supply moni- tor. the analog supply (av dd ) is continuously monitored by the ade7753. if the supply is less than 4v 5% then the ade7753 will go into an inactive state, i.e. no energy will be accumulated when the supply voltage is below 4v. this is useful to ensure correct device operation at power up and during power down. the power supply monitor has built-in hysteresis and filtering. this gives a high degree of immunity to false triggering due to noisy supplies. time av dd 0v 4v 5v ade7753 power-on inactive state inactive active inactive sag figure 12 - on-chip power supply monitor as can be seen from figure 12 the trigger level is nominally set at 4v. the tolerance on this trigger level is about 5%. the sag pin can also be used as a power supply monitor input to the mcu. the sag pin will go logic low when the ade7753 is in its inactive state. the power supply and decoupling for the part should be such that the ripple at av dd does not exceed 5v5% as specified for normal operation. line voltage sag detection in addition to the detection of the loss of the line voltage signal (zero crossing), the ade7753 can also be pro- grammed to detect when the absolute value of the line voltage drops below a certain peak value, for a number of line cycles. this condition is illustrated in figure 13 below. sagcyc[7:0] = 06h 6 half cycles saglvl[7:0] full scale channel 2 sag sag reset high when channel 2 exceeds saglvl[7:0] figure 13? ade7753 sag detection figure 13 shows the line voltage fall below a threshold which is set in the sag level register (saglvl[7:0]) for five line cycles. since the sag cycle register (sagcyc[7:0]) con- tains 03h the sag pin will go active low at the end of the fifth line cycle for which the line voltage falls below the threshold, if the dissag bit in the mode register is logic zero. as is the case when zero-crossings are no longer detected, the sag event is also recorded by setting the sag flag in the interrupt status register. if the sag enable bit is set to logic one, the irq logic output will go active low - see ade7753 interrupts . the sag pin will go logic high again when the absolute value of the signal on channel 2 exceeds the sag level set in the sag level register. this is shown in figure 13 when the sag pin goes high during the tenth line cycle from the time when the signal on channel 2 first dropped below the threshold level. sag level set the contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from lpf1, after it is shifted left by one bit. thus for example the nominal maximum code from lpf1 with a full scale signal on channel 2 is 2518h?see channel 2 sampling . shifting one bit left will give 4a30h. therefore writing 4ah to the sag level register will put the sag detection level at full scale. writing 00h will put the sag detection level at zero. the sag level register is compared to the most significant byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater. peak detection the ade7753 can also be programmed to detect when the absolute value of the voltage or the current channel of one phase exceeds a certain peak value. figure 14 illustrates the behavior of the peak detection for the voltage channel. vpklvl[7:0] v 2 pkv interrupt flag (bit 8 of status register) pkv reset low when rststatus register is read read rststatus register figure 14 - ade7753 peak detection both channel 1 and channel 2 are monitored at the same time. figure 14 shows a line voltage exceeding a threshold which is set in the voltage peak register (vpklvl[7:0]). the voltage peak event is recorded by setting the pkv flag in the interrupt status register. if the pkv enable bit is set to logic one in the interrupt mask register, the irq logic output will go active low. similarly, the current peak event is recorded by setting the pki flag in the ineterrupt status register?see ade7753 interrupts . peak level set the contents of the vpklvl and ipklvl registers are respectively compared to the absolute value of channel 1 and channel 2, after they are multiplied by 2.
ade7753 ?13? rev. prf 10/02 preliminary technical data ade7753 interrupts ade7753 interrupts are managed through the interrupt status register (status[15:0]) and the interrupt enable register (irqen[15:0]). when an interrupt event occurs in the ade7753, the corresponding flag in the status register is set to a logic one - see interrupt status register. if the enable bit for this interrupt in the interrupt enable register is logic one, then the irq logic output goes active low. the flag bits in the status register are set irrespective of the state of the enable bits. in order to determine the source of the interrupt, the system master (mcu) should perform a read from the status register with reset (rststatus[15:0]). this is achieved by carrying out a read from address 0ch. the irq output will go logic high on completion of the interrupt status register thus, for example, the nominal maximum code from the channel 1 adc with a full scale signal is 2851ech ?see channel 1 sampling . multiplying by 2 will give 50a3d8h. therefore, writing 50h to the ipklvl register will put the channel 1 peak detection level at full scale and set the current peak detection to its least sensitive value. writing 00h will put the channel 1 detection level at zero. the detection is done when the content of the ipklvl register is smaller than the incoming channel 1 sample. peak level record the ade7753 records the maximum absolute value reached by channel 1 and channel 2 in two different registers - ipeak and vpeak respectively. vpeak and ipeak are 24-bit unsigned registers. these registers are updated each time the absolute value of the waveform sample from the correspond- ing channel is above the value stored in the vpeak or ipeak register. the contents of the vpeak register corresponds to 2 times the maximum absolute value observed on the channel 2 input. the contents of ipeak represents the max absolute value observed on the channel 1 input. reading the rstvpeak and rstipeak registers will clear their re- spective contents after the read operation. irq t 1 jump to isr global int. mask set clear mcu int. flag read status with reset (05h) isr action (based on status contents) isr return global int. mask reset t 2 t 3 mcu int. flag set jump to isr mcu program sequence figure 15? ade7753 interrupt management read command?see interrupt timing . when carrying out a read with reset, the ade7753 is designed to ensure that no interrupt events are missed. if an interrupt event occurs just as the status register is being read, the event will not be lost and the irq logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. see the next section for a more detailed description. using the ade7753 interrupts with an mcu shown in figure 15 is a timing diagram which shows a suggested implementation of ade7753 interrupt manage- ment using an mcu. at time t 1 the irq line will go active low indicating that one or more interrupt events have oc- curred in the ade7753. the irq logic output should be tied to a negative edge triggered external interrupt on the mcu. on detection of the negative edge, the mcu should be configured to start executing its interrupt service routine (isr). on entering the isr, all interrupts should be disabled using the global interrupt enable bit. at this point the mcu external interrupt flag can be cleared in order to capture interrupt events which occur during the current isr. when the mcu interrupt flag is cleared a read from the status register with reset is carried out. this will cause the irq line to be reset logic high ( t 2 )?see interrupt timing . the status register contents are used to determine the source of the interrupt(s) and hence the appropriate action to be taken. if a subsequent interrupt event occurs during the isr, that event will be recorded by the mcu external interrupt flag being set again ( t 3 ). on returning from the isr, the global interrupt mask will be cleared (same instruction cycle) and the external interrupt flag will cause the mcu to jump to its isr once again. this will ensure that the mcu does not miss any external interrupts. interrupt timing the ade7753 serial interface section should be reviewed first before reviewing the interrupt timing. as previously de- cs sclk din t 1 t 11 t 11 t 9 db7 dout db0 db0 db7 000 read status register command 0 1 0 0 1 irq status register contents figure 16? ade7753 interrupt timing
ade7753 ?14? rev. prf 10/02 preliminary technical data temperature measurement ade7753 also includes an on-chip temperature sensor. a temperature measurement can be made by setting bit 5 in the mode register. when bit 5 is set logic high in the mode register, the ade7753 will initiate a temperature measure- ment on the next zero crossing. when the zero crossing on channel 2 is detected the voltage output from the tempera- ture sensing circuit is connected to adc1 (channel 1) for digitizing. the resultant code is processed and placed in the temperature register (temp[7:0]) approximately 26s later (24 clkin cycles). if enabled in the interrupt enable register (bit 5), the irq output will go active low when the temperature conversion is finished. please note that tempera- ture conversion will introduce a small amount of noise in the energy calculation. if temperature conversion is performed frequently (e.g. multiple times per second), a noticeable error will accumulate in the resulting energy calculation over time. the contents of the temperature register are signed (2's complement) with a resolution of approximately 1 lsb/c. the temperature register will produce a code of 00h when the ambient temperature is approximately 70c. the tempera- ture measurement is uncalibrated in the ade7753 and has an offset tolerance that could be as high as 20c. ade7753 analog to digital conversion the analog-to-digital conversion in the ade7753 is carried out using two second order sigma-delta adcs. for simplic- ity reason, the block diagram in figure 17 shows a first order sigma-delta adc. the converter is made up of two parts: the sigma-delta modulator and the digital low pass filter. v ref + - ....10100101...... digital low pass filter  e mclk/4 integrator 1-bit dac latched comparator + - r c analog low pass filter 24 figure 17? first order sigma-delta ( ? ) adc a sigma-delta modulator converts the input signal into a continuous serial stream of 1's and 0's at a rate determined by the sampling clock. in the ade7753 the sampling clock is equal to clkin/4. the 1-bit dac in the feedback loop is driven by the serial data stream. the dac output is sub- tracted from the input signal. if the loop gain is high enough the average value of the dac output (and therefore the bit stream) will approach that of the input signal level. for any given input value in a single sampling interval, the data from the 1-bit adc is virtually meaningless. only when a large number of samples are averaged will a meaningful result be obtained. this averaging is carried out in the second part of the adc, the digital low pass filter. by averaging a large number of bits from the modulator the low pass filter can produce 24-bit data words which are proportional to the input signal level. the sigma-delta converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. the first is over-sampling. by over sampling we mean that the signal is sampled at a rate (frequency) which is many times higher than the bandwidth of interest. for example the sampling rate in the ade7753 is clkin/4 (894khz) and the band of interest is 40hz to 2khz. over- sampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. with the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered?see figure 18. however, oversampling alone is not an efficient enough method to improve the signal to noise ratio (snr) in the band of interest. for example, an oversampling ratio of 4 is required just to increase the snr by only 6db (1-bit). to keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. this is what happens in the sigma-delta modulator, the noise is shaped by the integrator which has a high pass type response for the quantization noise. the result is that most of the noise is at the higher frequencies where it can be removed by the digital low pass filter. this noise shaping is also shown in figure 18. frequency (hz) 0 447khz 894khz 2khz sampling frequency shaped noise antialias filter (rc) digital filter noise signal fre q uenc y ( hz ) 0 447khz 894khz 2khz noise signal high resolution output from digital lpf figure 18? noise reduction due to oversampling & noise shaping in the analog modulator scribed, when the irq output goes low the mcu isr must read the interrupt status register in order to determine the source of the interrupt. when reading the status register contents, the irq output is set high on the last falling edge of sclk of the first byte transfer (read interrupt status register command). the irq output is held high until the last bit of the next 15-bit transfer is shifted out (interrupt status register contents)? see figure 16. if an interrupt is pending at this time, the irq output will go low again. if no interrupt is pending the irq output will stay high. antialias filter figure 17 also shows an analog low pass filter (rc) on the input to the modulator. this filter is present to prevent aliasing. aliasing is an artifact of all sampled systems. basically it means that frequency components in the input signal to the adc which are higher than half the sampling rate of the adc will appear in the sampled signal at a
ade7753 ?15? rev. prf 10/02 preliminary technical data frequency below half the sampling rate. figure 19 illustrates the effect. frequency components (arrows shown in black) above half the sampling frequency (also know as the nyquist frequency, i.e., 447khz) get imaged or folded back down below 447khz (arrows shown in grey). this will happen with all adcs regardless of the architecture. in the example shown, only frequencies near the sampling frequency, i.e., 894khz, will move into the band of interest for metering, i.e, 40hz - 2khz. this allows the usage of very simple lpf (low pass filter) to attenuate high frequency (near 900khz) noise and prevents distortion in the band of interest. for conven- tional current sensor, a simple rc filter (single pole lpf) with a corner frequency of 10khz will produce an attenuation of approximately 40dbs at 894khz?see figure 18. the 20db per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensor. for di/dt sensor such as rogowski coil, however, the sensor has 20db per decade gain. this will neutralize the -20db per decade attenuation produced by the simple lpf. therefore, when using a di/dt sensor, care should be taken to offset the 20db per decade gain coming from the di/dt sensor. one simple approach is to cascade two rc filters to produce the -40db per decade attenuation needed. fre q uenc y ( hz ) aliasing effects 0 447khz 894khz 2khz image frequencies sampling frequency figure 19 ?adc and signal processing in channel 1 adc transfer function below is an expression which relates the output of the lpf in the sigma-delta adc to the analog input signal level. both adcs in the ade7753 are designed to produce the same output code for the same input signal level. 144 , 262 0492 . 3 ) ( = out in v v adc code therefore with a full scale signal on the input of 0.5v and an internal reference of 2.42v, the adc output code is nomi- nally 165,151 or 2851fh. the maximum code from the adc is 262,144, this is equivalent to an input signal level of 0.794v. however for specified performance it is not recommended that the full-scale input signal level of 0.5v be exceeded. ade7753 reference circuit shown below in figure 20 is a simplified version of the reference output circuitry. the nominal reference voltage at the ref in/out pin is 2.42v. this is the reference voltage used for the adcs in the ade7753. however, channel 1 has three input range selections which are selected by dividing down the reference value used for the adc in channel 1. the reference value used for channel 1 is divided down to ? and ? of the nominal value by using an internal resistor divider as shown in figure 20. ptat 60 a 1.7k  12.5k  12.5k  12.5k  12.5k  2.5v 2.42v ref in/out reference input to adc channel 1 (range select) 2.42v, 1.21v, 0.6v maximum load = 10 a output impedance 6k  figure 20 ?ade7753 reference circuit ouput the ref in/out pin can be overdriven by an external source, e.g., an external 2.5v reference. note that the nominal reference value supplied to the adcs is now 2.5v not 2.42v. this has the effect of increasing the nominal analog input signal range by 2.5/2.42 100% = 3% or from 0.5v to 0.5165v. the voltage of ade7753 reference drifts slightly with temperature?see ade7753 specifications for the temperature coefficient specification (in ppm/c) . the value of the temperature drift varies from part to part. since the reference is used for the adcs in both channel 1 and 2, any x % drift in the reference will result in 2 x % deviation of the meter accuracy. the reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter. however, if guaranteed temperature performance is needed, one needs to use an external voltage reference. alternatively, the meter can be calibrated at multiple temperatures. real time compensa- tion can be easily achieved using the on the on-chip temperature sensor. channel 1 adc figure 21 shows the adc and signal processing chain for channel 1. in waveform sampling mode the adc outputs a signed 2?s complement 24-bit data word at a maximum of 27.9ksps (clkin/128). with the specified full scale ana- log input signal of 0.5v (or 0.25v or 0.125v ? see analog inputs section) the adc will produce an output code which is approximately between 2851ech (+2,642,412 decimal) and d7ae14h (-2,642,412 decimal). this is illustrated in figure 21. channel 1 sampling the waveform samples may also be routed to the wave- form register (mode[14:13] = 1,0) to be read by the system master (mcu). in waveform sampling mode the wsmp bit (bit 3) in the interrupt enable register must also be set to logic one. the active, apparent power and energy calculation will remain uninterrupted during waveform sam- pling. when in waveform sample mode, one of four output sample rates may be chosen by using bits 11 and 12 of the mode register (wavsel1,0). the output sample rate may be 27.9ksps, 14ksps, 7ksps or 3.5ksps?see mode register . the interrupt request output irq signals a new sample
ade7753 ?16? rev. prf 10/02 preliminary technical data availability by going active low. the timing is shown in figure 22. the 24-bit waveform samples are transferred from the ade7753 one byte (8-bits) at a time, with the most significant byte shifted out first. the 24-bit data word is right justified - see ade7753 serial interface . 0 0 0 01 hex irq din dout sclk read from waveform channel 1 data - 24 bits sign figure 22 ? waveform sampling channel 1 the interrupt request output irq stays low until the interrupt routine reads the reset status register - see ade7753 interrupt . channel 1 rms calculation root mean square (rms) value of a continuous signal v(t) is defined as: ()   = t rms dt t v t v 0 2 1 (1) for tie apling ignal r calculation involve uaring te ignal taing te average an otaining te uare root n i rms i v n v 1 2 ) ( 1 (2) a3 calculate iultaneoul te r value or cannel 1 an cannel 2 in ierent regiter figure 23 ow te etail o te ignal proceing cain or te r calculation on cannel 1 e cannel 1 r value i procee ro te aple ue in te cannel 1 waveor apling oe e cannel 1 r value i tore in an unigne 24it regiter (r) one o te cannel 1 pf 1p 1 ac 1 pa1 1 2 4 1 rfrc 242 121 1 analog nput range 2 12 2 313 1 1 21c a14 ac output wor range 21c a14 cannel 1 (current aveor) ata range ac a rac por cacao afor ap rr a2 a43 1f3c 1c4 cannel 1 (current aveor) ata range ater integrator () a raor a raor a fca op aa aa p o a frc ca raor a a 2ca frc rpo a op o frr aa 1c 31f cannel 1 (current aveor) ata range ater ntegrator () crr r (r) cacao figure 21 ac an ignal proceing in cannel 1 r regiter i euivalent to one o a cannel 1 waveor aple e upate rate o te cannel 1 r eaureent i c4 24 pf3 current ignal i(t) 21c a14 r (t) 1c23 r cannel 1  sign 2 25 2 26 2 27 2 17 2 16 2 15 irmsos[11:0] 24 hpf figure 23 - channel 1 rms signal processing with the specified full scale analog input signal of 0.5v, the adc will produce an output code which is approximately 2,642,412d?see channel 1 adc . the equivalent rms val- ues of a full-scale ac signal is 1,868,467d (1c82b3h). channel 1 rms offset compensation the ade7753 incorporates a channel 1 rms offset compen- sation register (irmsos). this is 12-bit signed registers which can be used to remove offset in the channel 1 rms calculation. an offset may exist in the rms calculation due to input noises that are integrated in the dc component of v 2 (t). the offset calibration will allow the content of the irms register to be maintained at zero when no input is present on channel 1. 1 lsb of the channel 1 rms offset are equivalent to 32,768 lsb of the square of the channel 1 rms register. assuming that the maximum value from the channel 1 rms calcula- tion is 1,868,467d with full scale ac inputs, then 1 lsb of the channel 1 rms offset represents 0.46% of measurement error at -60db down of full scale. 32768 2 0 + = irmsos i i rms rms where i rmso is the rms measurement without offset correc- tion.
ade7753 ?17? rev. prf 10/02 preliminary technical data directly to the multiplier and is not filtered. a hpf is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation. when in waveform sample mode, one of four output sample rates can be chosen by using bits 11 and 12 of the mode register. the available output sample rates are 27.9ksps, 14ksps, 7ksps or 3.5ksps? see mode register . the interrupt request output irq signals a sample availability by going active low. the timing is the same as that for channel 1 and is shown in figure 22. channel 2 rms calculation figure 26 shows the details of the signal processing chain for the rms calculation on channel 2. the channel 2 rms value is processed from the samples used in the channel 2 waveform sampling mode. the rms value will be slightly attenuated because of lpf1. channel 2 rms value is stored in the unsigned 24-bit vrms register. the update rate of the channel 2 rms measurement is clkin/4. with the specified full scale ac analog input signal of 0.5v, the outputs from the lpf1 swings between 2518h and dae8h at 60 hz- see channel 2 adc . the equivalent rms value of this full-scale ac signal is approximately 1,561,400 (17d338h) in the vrms register. lpf3 voltage signal - v(t) 2518h 0h dae8h vrms[23:0] 17d338h 00h channel 2 lpf1 s  sgn 2 9 2 8 2 2 2 1 2 0 vrmsos[11:0]  figure 26 - channel 2 rms signal processing channel 2 rms offset compensation the ade7753 incorporates a channel 2 rms offset compen- sation register (vrmsos). this is a 12-bit signed registers which can be used to remove offset in the channel 2 rms calculation. an offset may exist in the rms calculation due to input noises and dc offset in the input samples. the offset calibration allows the contents of the vrms register to be maintained at zero when no voltage is applied. 1 lsb of the channel 2 rms offset are equivalent to 1 lsb of the rms register. assuming that the maximum value from the channel 2 rms calculation is 1,561,400d with full scale ac inputs, then 1 lsb of the channel 2 rms offset represents 0.064% of measurement error at -60db down of full scale. vrmsos v v rmso rms + = where v rmso is the rms measurement without offset correc- tion. phase compensation when the hpf is disabled, the phase error between channel 1 and channel 2 is zero from dc to 3.5khz. when hpf is enabled, channel 1 has a phase response illustrated in figures 28 & 29. also shown in figure 30 is the magnitude response of the filter. as can be seen from the plots, the phase response is almost zero from 45hz to 1khz, this is all that is required in typical energy measurement applications. channel 2 adc channel 2 sampling in channel 2 waveform sampling mode (mode[14:13] = 1,1 and wsmp = 1) the adc output code scaling for channel 2 is not the same as channel 1. channel 2 waveform sample is a 16-bit word and sign extended to 24 bits. for normal operation, the differential voltage signal between v2p and v2n should not exceed 0.5v. with maximum voltage input (0.5v at pga gain of 1), the outputs from the adc swings between 2852h and d7aeh (10,322 deci- mal). however, before being passed to the waveform register, the adc output is passed through a single pole, low pass filter with a cutoff frequency of 140hz. the plots in figure 24 shows the magnitude and phase response of this filter. 10 1 10 2 10 3 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 gain (dbs) phase () frequency (hz) 60 hz, -0.73db 50 hz, -0.52db 60 hz, -23.2 50 hz, -19.7 figure 24 ? magnitude & phase response of lpf1 the lpf1 has the effect of attenuating the signal. for example if the line frequency is 60hz, then the signal at the output of lpf1 will be attenuated by about 8%. () 0.73db 0.919 140hz 60hz 1 1 h(f) 2 ? = = + = note lpf1 does not affect the power calculation. the signal processing chain in channel 2 is illustrated in figure 25. v2p v2n adc 2 pga2 x1, x2, x4, x8, x16 reference gain[7:5] v2 v1 0v analog input range active and reactive energy calculation lpf1 0000h 2852h d7aeh lpf output word range vrms calculation and waveform sampling (peak/sag/zx) 2518h dae8h 0.5v, 0.25v, 0.125v, 62.5mv, 31.25mv 2.42v figure 25 ? adc and signal processing in channel 2 unlike channel 1, channel 2 has only one analog input range (1v differential). however like channel 1, channel 2 does have a pga with gain selections of 1, 2, 4, 8 and 16. for energy measurement, the output of the adc is passed
ade7753 ?18? rev. prf 10/02 preliminary technical data however, despite being internally phase compensated the ade7753 must work with transducers which may have inherent phase errors. for example a phase error of 0.1 to 0.3 is not uncommon for a ct (current transformer). these phase errors can vary from part to part and they must be corrected in order to perform accurate power calculations. the errors associated with phase mismatch are particularly noticeable at low power factors. the ade7753 provides a means of digitally calibrating these small phase errors. the ade7753 allows a small time delay or time advance to be introduced into the signal processing chain in order to compensate for small phase errors. because the compensa- tion is in time, this technique should only be used for small phase errors in the range of 0.1 to 0.5. correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. the phase calibration register (phcal[5:0]) is a 2?s complement signed single byte register which has values ranging from 21h (-31 in decimal) to 1fh (31 in decimal). the register is centered at 0dh, so that writing 0dh to the register gives zero delay. by changing the phcal register, the time delay in the channel 2 signal path can change from ?100.8s to +33.6s (clkin = 3.579545mhz). one lsb is equivalent to 2.22s time delay or advance. with a line frequency of 60hz this gives a phase resolution of 0.048 at the fundamental (i.e., 360 2.22s 60hz). figure 27 illustrates how the phase compensation is used to remove a 0.1 phase lead in channel 1 due to the external transducer. in order to cancel the lead (0.1) in channel 1, a phase lead must also be introduced into channel 2. the resolution of the phase adjustment allows the introduction of a phase lead in increment of 0.048. the phase lead is achieved by introduc- ing a time advance into channel 2. a time advance of 4.48s is made by writing -2 (0bh) to the time delay block, thus reducing the amount of time delay by 4.48s, or equivalently, a phase lead of approximately 0.1 at line frequency of 60hz. 0bh represents -2 because the register is centered with zero at 0dh. 0 001 1 01 5 v2p v2n adc 2 pga2 1 v2 24 lpf2 hpf v1p v1n adc 1 pga1 v1 24 phcal[5:0] delay block 4.48 s / lsb -100 s to +34 s v1 v2 60hz channel 2 delay reduced by 4.48 s (0.1 8 lead at 60hz) 0bh in phcal[5:0] v2 v1 0.1 8 60hz figure 27 ? phase calibration 10 2 10 3 10 4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 frequency-hz phase-degrees figure 28 ? combined phase response of the hpf & phase compensation (10hz to 1khz) 40 45 50 55 60 65 70 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 frequency-hz phase-degrees figure 29 ? combined phase response of the hpf & phase compensation (40hz to 70hz) 40 45 50 55 60 65 70 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 frequency - hz gain-db figure 30 ? combined gain response of the hpf & phase compensation active power calculation power is defined as the rate of energy flow from source to load. it is defined as the product of the voltage and current waveforms. the resulting waveform is called the instanta- neous power signal and it is equal to the rate of energy flow at every instant of time. the unit of power is the watt or joules/
ade7753 ?19? rev. prf 10/02 preliminary technical data sec. equation 3 gives an expression for the instantaneous power signal in an ac system. () () t v t v  sin 2 = (1) () () t i t i  sin 2 = (2) where v = rms voltage, i = rms current. () () () () ( ) t t p t i t v t p  cos vi vi ? = = ( 3 ) the average power over an integral number of line cycles (n) is given by the expression in equation 4. () 0 1 nt pptdtv i nt ==  (4) where t is the line cycle period. p is referred to as the active or real power. note that the active power is equal to the dc component of the instanta- neous power signal p(t) in equation 3 , i.e., vi. this is the relationship used to calculate active power in the ade7753. the instantaneous power signal p(t) is generated by multiply- ing the current and voltage signals. the dc component of the instantaneous power signal is then extracted by lpf2 (low pass filter) to obtain the active power information. this process is illustrated graphically in figure 31. voltage current instantaneous power signal active real power signal = v x i v. i. 00000h 19999ah ccccdh v(t) = 2 v sin(  t) i(t) = 2 i sin(  t) p(t) = v i-v i cos(2  t) figure 31 C active power calculation ince pf2 oe not ave an ieal ric wall reuenc reponeee figure 32 te active power ignal will ave oe ripple ue to te intantaneou power ignal i ripple i inuoial an a a reuenc eual to twice te line reuenc ince te ripple i inuoial in nature it will e reove wen te active power ignal i integrate to calculate nerg ee nerg calculation frequency 1.0hz 3.0hz 10hz 30hz 100hz -24 -20 -16 -12 -8 -4 0 dbs figure 32 ?frequency response of lpf2 figure 33 shows the signal processing chain for the activepower calculation in the ade7753. as explained, the active power is calculated by low pass filtering the instanta- neous power signal. note that for when reading the waveform samples from the output of lpf2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (wgain[11:0]). the gain is adjusted by writing a 2?s complement 12-bit word to the watt gain register. below is the expression that shows how the gain adjustment is related to the contents of the watt gain register.
        + = 12 2 1 wgain power active wgain output for example when 7ffh is written to the watt gain register the power output is scaled up by 50%. 7ffh = 2047d, 2047/2 12 = 0.5. similarly, 800h = -2048 dec (signed 2?s complement) and power output is scaled by ?50%. shown in figure 34 is the maximum code (in hex) output range for the active power signal (lpf2). note that the output range changes depending on the contents of the watt gain register. the minimum output range is given when the watt gain register contents are equal to 800h, and the hpf lpf2 current signal - i(t) voltage signal - v(t) instantaneous power signal - p(t) multiplier active power signal - p ccccdh i v 19999ah 000000h wgain[11:0]  + 2 -6 2 -7 apos[15:0] sgn 2 -8 2 6 2 5 32 24 + for energy accumulation for waveform sampling 19999h 24 figure 33 ? active power signal processing
ade7753 ?20? rev. prf 10/02 preliminary technical data energy calculation as stated earlier, power is defined as the rate of energy flow. this relationship can be expressed mathematically as equation 5. p= de dt (5) where p = power and e = energy. conversely energy is given as the integral of power.  = p dt e (6) the ade7753 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal non-readable 56-bit energy register. the active energy register (aenergy[23:0]) represents the upper 24 bits of this internal register. this discrete time accumulation or summation is equivalent to integration in continuous time. equation 7 below expresses the relationship       = =    =  1 0 ) ( ) ( n t t nt p dt t p e lim (7) where n is the discrete time sample number and t is the sample period. 4 clkin time (nt) waveform register values output lpf2 t lpf2 outputs from the lpf2 are accumulated (integrated) in the internal active energy register + +  active power signal - p* current channel voltage channel apos [15:0] 46 0 aenergy[23:0] wdiv[7:0] 23 0 wgain[11:0] upper 24 bits are accessible through aenergy[23:0] register figure 35 ? ade7753 active energy calculation the discrete time sample period (t) for the accumulation register in the ade7753 is 1.1s (4/clkin). as well as calculating the energy this integration removes any sinusoi- dal components which may be in the active power signal. figure 35 shows a graphical representation of this discrete time integration or accumulation. the active power signal in the waveform register is continuously added to the internal active energy register. this addition is a signed addition, therefore negative energy will be subtracted from the active energy contents. the output of the multiplier is divided by wdiv. if the value in the wdiv register is equal to 0 then the internal active energy register is divided by 1. wdiv is an 8-bit unsigned register. after dividing by wdiv, the active energy is accumulated in a 48-bit internal energy accumulation regis- ter. the upper 24 bit of this register is accessible through a read to the active energy register (aenergy[23:0]). a read to the raenergy register will return the content of the aenergy register and the upper 24-bit of the internal register is clear after a read to aenergy register. as shown in figure 35, the active power signal is accumu- lated in an internal 48-bit signed register. the active power signal can be read from the waveform register by setting mode[14:13] = 0,0 and setting the wsmp bit (bit 3) in the interrupt enable register to 1. like the channel 1 and channel 2 waveform sampling modes the waveform date is available at sample rates of 27.9ksps, 14ksps, 7ksps or 3.5ksps?see figure 22. figure 36 shows this energy accumulation for full scale signals (sinusoidal) on the analog inputs. the three curves displayed, illustrate the minimum period of time it takes the energy register to roll-over when the active power gain register contents are 7ffh, 000h and 800h. the watt gain register is used to carry out power calibration in the ade7753. as shown, the fastest integration time will occur when the watt gain register is set to maximum full scale, i.e., 7ffh. 00,0000h 7f,ffffh 80,0000h 3f,ffffh 40,0000h aenergy[23:0] time (minutes) wgain = 7ffh wgain = 000h wgain = 800h 6.2 12.5 4 8 figure 36 - energy register roll-over time for full-scale power (minimum & maximum power gain) note that the energy register contents will roll over to full- scale negative (800000h) and continue increasing in value when the power or energy flow is positive - see figure 36. conversely if the power is negative the energy register would under flow to full scale positive (7fffffh) and continue decreasing in value. by using the interrupt enable register, the ade7753 can be configured to issue an interrupt ( irq ) when the active energy register is half-full (positive or negative) or when an over/under flow occurs. integration time under steady load as mentioned in the last section, the discrete time sample period (t) for the accumulation register is 1.1s (4/clkin). maximum range is given by writing 7ffh to the watt gain register. this can be used to calibrate the active power (or energy) calculation in the ade7753. 00000h ccccdh f33333h wgain[11:0] 000h 7ffh 800h active power calibration range positive power negative power active power output 66666h f9999ah 133333h eccccdh figure 34 C active power calculation output range
ade7753 ?21? rev. prf 10/02 preliminary technical data power offset calibration the ade7753 also incorporates an active power offset register (apos[15:0]). this is a signed 2?s complement 16- bit register which can be used to remove offsets in the active power calculation? see figure 33 . an offset may exist in the power calculation due to cross talk between channels on the pcb or in the ic itself. the offset calibration will allow the contents of the active power register to be maintained at zero when no power is being consumed. two hundred fifty six lsbs (apos=0100h) written to the active power offset register are equivalent to 1 lsb in the waveform sample register. assuming the average value outputs from lpf2 is ccccdh (838,861 in decimal) when inputs on channels 1 and 2 are both at full-scale. at -60db down on channel 1 (1/1000 of the channel 1 full-scale input), the average word value outputs from lpf2 is 838.861 (838,861/1,000). 1 lsb in the lpf2 output has a measure- ment error of 1/838.861 100% = 0.119% of the average value. the active power offset register has a resolution equal to 1/256 lsb of the waveform register, hence the power offset correction resolution is 0.00047%/lsb (0.119%/ 256) at -60db. energy to frequency conversion ade7753 also provides energy to frequency conversion for calibration purposes. after initial calibration at manufactur- ing, the manufacturer or end customer will often verify the energy meter calibration. one convenient way to verify the meter calibration is for the manufacturer to provide an output frequency which is proportional to the energy or active power under steady load conditions. this output frequency can provide a simple, single wire, optically isolated interface to external calibration equipment. figure 37 illustrates the energy-to-frequency conversion in the ade7753. cf 0 11 cfnum[11:0] energy 0 11 cfden[11:0] dfc 0 23 aenergy[23:0] figure 37? ade7753 energy to frequency conversion a digital to frequency converter (dfc) is used to generate the cf pulsed output. the dfc generates a pulse each time one lsb in the active energy register is accumulated. an output pulse is generated when (cfden+1)/(cfnum+1) number of pulses are generated at the dfc output. under steady load conditions the output frequency is proportional to the active power. the maximum output frequency, with ac input signals at full-scale and cfnum=00h & cfden=00h, is approxi- mately 23 khz. the ade7753 incorporates two registers, cfnum[11:0] and cfden[11:0], to set the cf frequency. these are unsigned 12-bit registers which can be used to adjust the cf frequency to a wide range of values. these frequency scaling registers are 12-bit registers which can scale the output frequency by 1/2 12 to 1 with a step of 1/2 12 . if the value zero is written to any of these registers, the value one would be applied to the register. the ratio (cfnum+1)/ (cfden+1) should be smaller than one to assure proper operation. if the ratio of the registers (cfnum+1)/ (cfden+1) is greater than one, the register values would be adjust to a ratio (cfnum+1)/(cfden+1) of one. for example if the output frequency is 1.562khz while the contents of cfdenare zero (000h), then the output frequency can be set to 6.1hz by writing ffh to the cfden register. note that for values where cfden>cfnum, the performance of the cf frequency is not guaranteed. cfnum should always be set to a value less than cfden. the output frequency will have a slight ripple at a frequency equal to twice the line frequency. this is due to imperfect filtering of the instantaneous power signal to generate the active power signal ? see active power calculation . equation 3 gives an expression for the instantaneous power signal. this is filtered by lpf2 which has a magnitude response given by equation 9. 2 2 9 . 8 1 1 ) ( f f h + = (9) the active power signal (output of lpf2) can be rewritten as. () t f f vi vi t p l l  4 cos 9 . 8 2 1 ) ( 2               
  + ? = (10) where f l is the line frequency (e.g., 60hz) from equation 6 () t f f f vi vit t e l l l   4 sin 9 . 8 2 1 4 ) ( 2               
  + ? = (11) from equation 11 it can be seen that there is a small ripple in the energy calculation due to a sin(2  t) component. this is shown graphically in figure 38. the active energy calculation is shown by the dashed straight line and is equal with full-scale sinusoidal signals on the analog inputs and the wgain register set to 000h, the average word value from each lpf2 is ccccdh - see figure 31. the maximum positive value which can be stored in the internal 47-bit register is 2 46 - 1 or 7fff,ffff,ffffh before it overflows, the integration time under these conditions with wdiv=0 is calculated as follows: s s s c cccd h ffffh ffff fff t ime min 12 . 3 = 5 . 187 = 12 . 1 , , 3 = when wdiv is set to a value different from 0, the integration time varies as shown on equation 8. time = time wdiv=0 x wdiv (8)
ade7753 ?22? rev. prf 10/02 preliminary technical data to v x i x t. the sinusoidal ripple in the active energy calculation is also shown. since the average value of a sinusoid is zero, this ripple will not contribute to the energy calculation over time. however, the ripple can be observed in the frequency output, especially at higher output frequen- cies. the ripple will get larger as a percentage of the frequency at larger loads and higher output frequencies. the reason is simply that at higher output frequencies the integra- tion or averaging time in the energy-to-frequency conversion process is shorter. as a consequence some of the sinusoidal ripple is observable in the frequency output. choosing a lower output frequency at cf for calibration can significantly reduce the ripple. also averaging the output frequency by using a longer gate time for the counter will achieve the same results. t e(t) ? r s t u v w vi 4. (1+ 2. / 8.9hz) sin(4.   . ..) ff ft ll l vit figure 38 ? output frequency ripple line cycle energy accumulation mode in line cycle energy accumulation mode, the energy accumulation of the ade7753 can be synchronized to the channel 2 zero crossing so that active energy can be accumu- lated over an integral number of half line cycles. the advantage of summing the active energy over an integer number of half line cycles is that the sinusoidal component in the active energy is reduced to zero. this eliminates any ripple in the energy calculation. energy is calculated more accurately and in a shorter time because integration period can be shortened. by using the line cycle energy accumula- tion mode, the energy calibration can be greatly simplified and the time required to calibrate the meter can be signifi- cantly reduced. the ade7753 is placed in line cycle energy accumulation mode by setting bit 7 (cycmode) in the mode register. in line cycle energy accumulation mode the ade7753 accumulates the active power signal in the laenergy register (address 04h) for an integral number of line cycles, as shown in figure 39. the number of half line cycles is specified in the linecyc register (address 1ch). the ade7753 can accumulate active power for up to 65,535 half line cycles. because the active power is integrated on an integral number of line cycles, at the end of a line cycle energy accumulation cycle the cycend flag in the interrupt status register is set (bit 2). if the cycend enable bit in the interrupt enable register is enabled, the irq output will also go active low. thus the irq line can also be used to signal the completion of the line cycle energy accumulation. an- other calibration cycle will start as long as the cycmode bit in the mode register is set. note that the result of the first calibration is invalid and should be ignored. the result of all subsequent line cycle accumulation is correct. from equations 6 and 10. ()                 
  + ? = nt nt dt t f f vi dt vi t e 0 2 0 2 cos 9 . 8 1 ) (  (12) where n is a integer and t is the line cycle period. since the sinusoidal component is integrated over a integer number of line cycles its value is always zero. therefore:  + = nt vidt e 0 0 (13) e(t) vint = (14) + +  calibration control linecyc[14:0] output from lpf2 lpf1 from channel 2 adc zero cross detection accumulate active energy in internal register and update the laenergy register at the end of linecyc line-cycles 46 0 laenergy[23:0] wdiv[7:0] 23 0 figure 39 ? energy calculation in line cycle energy accu- mulation mode note that in this mode, the 16-bit linecyc register can hold a maximum value of 65,535. in other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65,535 half line cycles. at 60hz line frequency, it translates to a total duration of 65,535 / 120hz = 546 seconds. positive only accumulation mode in positive only accumulation mode, the energy accumula- tion is done only for positive power, ignoring any occurrence of negative power above or below the no load threshold as shown in figure 40. the ade7753 is placed in positive only active power irq active energy pneg ppos pneg interrupt status registers no-load threshold no-load threshold pneg ppos ppos figure 40 ? energy accumulation in positive only accumulation mode
ade7753 ?23? rev. prf 10/02 preliminary technical data accumulation mode by setting the msb of the mode register (mode[15]). the default setting for this mode is off. transitions in the direction of power flow, going from negative to positive or positive to negative, set the irq pin to active low if the interrupt enable register is enabled. the interrupt status registers, ppos and pneg, show which transition has occurred. see ade7753 register descriptions. no load threshold the ade7753 includes a "no load threshold" feature that will eliminate any creep effects in the meter. the ade7753 accomplishes this by not accumulating energy if the multi- plier output is below the "no load threshold". this threshold is 0.001% of the full-scale output frequency of the multiplier. compare this value to the iec1036 specification which states that the meter must start up with a load equal to or less than 0.4% ib. this standard translates to .0167% of the full-scale output frequency of the multiplier. reactive power calculation reactive power is defined as the product of the voltage and current waveforms when one of this signal is phase shifted by 90o. the resulting waveform is called the instantaneous reactive power signal. equation 17 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90o. ) sin( 2 ) (   + = t v t v (15) ) t sin( i ) t ( ' i ) t sin( i ) t ( i 2 2 2  +  =  = (16) where  is the phase difference between the voltage and current channel, v = rms voltage and i = rms current. ) ( ' ) ( ) ( t i t v t rp = ) 2 sin( ) sin( ) (    + + = t vi vi t rp (17) the average power over an integral number of line cycles (n) is given by the expression in equation 18.  = = nt vi dt t rp nt rp 0 ) sin( ) ( 1  (18) where t is the line cycle period. rp is referred to as the reactive power. note that the reactive power is equal to the dc component of the instantaneous reactive power signal rp(t) in equation 17. this is the relationship used to calculate reactive power in the ade7753. the instantaneous reactive power signal rp(t) is generated by multiplying the channel 1 and channel 2. in this case, the phase of the channel 1 is shifted by +90o. the dc component of the instantaneous reactive power signal is then extracted by a low pass filter to obtain the reactive power information. figure 41 shows the signal processing in the reactive power calculation in the ade7753. + +  calibration control linecyc[14:0] lpf1 from channel 2 adc zero cross detection accumulate active energy in internal register and update the lvarenergy register at the end of linecyc line cycles 47 0 lvarenergy [23:0] 23 0 instantaneous reactive power signal - rp(t) multiplier 90 degree phase shift i  2 v figure 41 - reactive power signal processing the features of the reactive energy accumulation are the same as the line active energy accumulation. the number of half line cycles is specified in the linecyc register. linecyc is an unsigned 16-bit register. the ade7754 can accumulate reactive power for up to 65535 combined half cycles. at the end of an energy calibration cycle the cycend flag in the interrupt status register is set. if the cycend mask bit in the interrupt mask register is enabled, the irq output will also go active low. thus the irq line can also be used to signal the end of a calibration. the ade7753 accumulates the reactive power signal in the lvarenergy register for an integer number of half cycles, as shown in figure 41. the reactive energy accumulation in the ade7753 not only provides the reactive energy calculated using the phase shift method, it is also useful to provide the sign of the reactive power if it is desirable to use triangular method to calculate reactive power. the ade7753 also provides an accurate measurement of the apparent power. the user can choose to determine reactive energy through the mathematical rela- tionship between apparent, active and reactive power. the sign of the reactive energy can be found by reading the result from the lvarenergy register at the end of a reactive energy accumulation cycle. 2 2 ) (re re energy active energy apparent energy active sign energy active ? = apparent power calculation apparent power is defined as the amplitude of the vector sum of the active and reactive powers -see figure 42. the angle  between the active power and the apparent power generally represents the phase shift due to non-resistive loads. for single phase applications,  represents the angle between the voltage and the current signals. equation 20 gives an expres- sion of the instantaneous power signal in an ac system with a phase shift.
ade7753 ?24? rev. prf 10/02 preliminary technical data reactive power active power apparen t power  figure 42 - power triangle () ()    + = = t t i t t v sin i 2 ) ( sin v 2 ) ( rms rms (19) ) 2 cos( ) cos( ) ( ) ( ) ( ) (    + ? = = t i v i v t p t i t v t p rms rms rms rms (20) the apparent power (ap) is defined as v rms x i rms . this expression is independent from the phase angle between the current and the voltage. figure 43 illustrates graphically the signal processing in each phase for the calculation of the apparent power in the ade7753. current rms signal - i(t) voltage rms signal - v(t) multiplier apparent power signal - p i rms v rms 00h 00h ad055h vagain 1c82b3h 17d338h figure 43 - apparent power signal processing the gain of the apparent energy can be adjusted by using the multiplier and va gain register (vagain[11:0]). the gain is adjusted by writing a 2?s complement, 12-bit word to the vagain register. below is the expression that shows how the gain adjustment is related to the contents of the va gain register.
        + = 12 2 1 vagain power apparent vagain output for example when 7ffh is written to the va gain register the power output is scaled up by 50%. 7ffh = 2047d, 2047/2 12 = 0.5. similarly, 800h = -2047 dec (signed 2?s complement) and power output is scaled by ?50%. the apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ade7753. shown in figure 44 is the maximum code (hexadecimal) output range of the apparent power signal. note that the output range changes depending on the contents of the apparent power gain registers. the minimum output range is given when the apparent power gain register content is equal to 800h and the maximum range is given by writing 7ffh to the apparent power gain register. this can be used to calibrate the apparent power (or energy) calcu- lation in the ade7753 -see apparent power calculation . 00000h ad055h 103880h 5682bh vagain[11:0] 000h 7ffh 800h apparent power calibration range apparent power 100% fs apparent power 150% fs apparent power 50% fs voltage and current channel inputs: 0.5v / gain figure 44- apparent power calculation output range apparent power offset calibration each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value -see channel 1 rms calculation and channel 2 rms calculation . the channel 1 and channel 2 rms values are then multiplied together in the apparent power signal processing. as no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. the offset compensa- tion of the apparent power measurement is done by calibrating each individual rms measurements. apparent energy calculation the apparent energy is given as the integral of the apparent power. dt t power apparent energy apparent  = ) ( (21) the ade7753 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. the apparent energy register (vaenergy[23:0]) represents the upper 24 bits of this internal register. this discrete time accumu- lation or summation is equivalent to integration in continuous time. equation 23 below expresses the relationship       =   =  0 0 ) ( n t t nt power apparent lim energy apparent (22) where n is the discrete time sample number and t is the sample period. the discrete time sample period (t) for the accumulation register in the ade7753 is 1.1s (4/clkin). figure 44 shows a graphical representation of this discrete time integration or accumulation. the apparent power signal is continuously added to the internal register. this addition is a signed addition even if the apparent energy remains theoretically always positive.
ade7753 ?25? rev. prf 10/02 preliminary technical data 46 0 + +  apparent power 00000h ad055h time (nt) t apparent power are accumulated (integrated) in the apparent energy register apparent power signal - p t 47 0 vaenergy[23:0] vadiv 23 0 figure 45- ade7753 apparent energy calculation the upper 52-bit of the internal register are divided by vadiv. if the value in the vadiv register is equal to 0 then the internal active energy register is divided by 1. vadiv is an 8-bit unsigned register. the upper 24-bit are then written in the 24-bit apparent energy register (vaenergy[23:0]). rvaenergy register (24 bits long) is provided to read the apparent energy. this register is reset to zero after a read operation. figure 45 shows this apparent energy accumulation for full scale signals (sinusoidal) on the analog inputs. the three curves displayed, illustrate the minimum time it takes the energy register to roll-over when the va gain registers content is equal to 7ffh, 000h and 800h. the va gain register is used to carry out an apparent power calibration in the ade7753. as shown, the fastest integration time will occur when the va gain register is set to maximum full scale, i.e., 7ffh. 40,0000h ff,ffffh 00,0000h 80,0000h 20,0000h vaenergy[23:0] time (minutes) vagain = 7ffh vagain = 000h vagain = 800h 14.8 4.9 7.4 11.1 figure 46- energy register roll-over time for full-scale power (minimum & maximum power gain) note that the apparent energy register contents roll-over to full-scale negative (80,0000h) and continue increasing in value when the power or energy flow is positive - see figure 46. by using the interrupt enable register, the ade7754 can be configured to issue an interrupt ( irq ) when the apparent energy register is half full (positive or negative) or when an over/under flow occurs. integration times under steady load as mentioned in the last section, the discrete time sample period (t) for the accumulation register is 1.1s (4/clkin). with full-scale sinusoidal signals on the analog inputs and the vagain register set to 000h, the average word value from apparent power stage is ad055h - see apparent power output range . the maximum value which can be stored in the apparent energy register before it over-flows is 2 24 or ff,ffffh. as the average word value is added to the internal register which can store 2 48 - 1 or 7fff,ffff,ffffh before it overflows, the integration time under these condi- tions with vadiv=0 is calculated as follows: min 8 . 4 1 = s 88 8 = s 1.2 ad055h ffffh ffff, 7fff, = time when vadiv is set to a value different from 0, the integra- tion time varies as shown on equation 23. time = time wdiv=0 x vadiv (23) line apparent energy accumulation the ade7753 is designed with a special apparent energy accumulation mode which simplifies the calibration process. by using the on-chip zero-crossing detection, the ade7753 accumulates the apparent power signal in the lvaenergy register for an integral number of half cycles, as shown in figure 47. the line apparent energy accumulation mode is always active. the number of half line cycles is specified in the lincyc register. lincyc is an unsigned 16-bit register. the ade7753 can accumulate apparent power for up to 65535 combined half cycles. because the apparent power is inte- grated on the same integral number of line cycles as the line active energy register, these two values can be compared easily. the active and apparent energy are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. at the end of an energy calibration cycle the cycend flag in the interrupt status register is set. if the cycend mask bit in the interrupt mask register is enabled, the irq output will also go active low. thus the irq line can also be used to signal the end of a calibration. the line apparent energy accumulation uses the same signal path as the apparent energy accumulation. the lsb size of these two registers is equivalent. + +  calibration control linecyc[15:0] apparent power lvaenergy register is updated every linecyc zero-crossings with the total apparent energy during that duration 46 lvaenergy[23:0] vadiv[7:0] 23 0 lpf1 from channel 2 adc zero crossing detection 0 figure 47 - ade7753 apparent energy calibration
ade7753 ?26? rev. prf 10/02 preliminary technical data calibrating the energy meter when calibrating the ade7753, the first step is to calibrate the frequency on cf to some required meter constant, e.g., 3200 imp/kwh. a convenient way to to determine the output frequency on cf is to use the line cycle energy accumulation mode. as shown in figure 37, dfc generates a pulse each time a lsb in the laenergy register is accumulated. cf frequency (before the cf frequency divider) can be conveniently determined by the following expression: time elasped r 0] registe : 3 laenergy[2 of content frequency cf = when the cycmode (bit 7) bit in the mode register is set to a logic one, energy is accumulated over an integer number of half line cycles. if the line frequency is fixed and the number of half cycles of integration is specified, the total elasped time can be calculated by the following: cycles half of number f 2 1 time elasped l = for example, at 60hz line frequency, the elasped time for 255 half cycles will be 2.125 seconds. rewriting the above in terms of contents of various ade7753 registers and line frequencies ( fl ): 0] : linecyc[15 fl 2 0] : 3 laenergy[2 frequency cf = (24) where f l is the line frequency. alternatively, cf frequency can be calculated based on the average lpf2 output. 27 2 clkin output lpf2 average = frequency c f (25) calibrating the frequency at cf when the frequency before frequency division is known, the pair of cf frequency divider registers (cfnum and cfden) can be adjusted to produce the required frequency on cf. in this example a meter constant of 3200 imp/kwh is chosen as an appropriate constant. this means that under a steady load of 1kw, the output frequency on cf would be, hz kwh imp cf frequency 8888 . 0 3600 3200 sec 60 min 60 / 3200 ) ( = = = assuming the meter is set up with a test current (basic current) of 20a and a line voltage of 220v for calibration, the load is calculated as 220v 20a = 4.4kw. therefore the expected output frequency on cf under this steady load condition would be 4.4 0.8888hz = 3.9111hz. under these load conditions the transducers on channel 1 and channel 2 should be selected such that the signal on the voltage channel should see approximately half scale and the signal on the current channel about 1/8 of full scale (assuming a maximum current of 80a). assuming at line frequency of 60hz, energy is accumulated over ffh number of half line cycles, the resulting content of the laenergy register will be approximately 2971.4 (decimal). cf frequency is there- fore calculated to be: 1398.3h z = 255 60 2 4 . 971 2 = (cf) f requency alternatively, the average value from lpf2 under this con- dition is approximately 1/16 of the full-scale level. as described previously, the average lpf2 output at full-scale ac input is ccccd (hex) or 838,861 (decimal). at 1/16 of full-scale, the lpf2 output is then 52,428.81. then using digital to frequency conversion, the frequency under this load is calculated as: h z 3 . 398 1 = 2 z 3.579545mh 52428.81 = cf) f requency( 27 this is the frequency with the contents of the cfnum and cfden registers equal to 000h. the desired frequency out is 3.9111hz. therefore, the cf frequency must be divided by 2797/3.9111hz or 357.5 decimal. this is achieved by loading the pair of cf divider registers with the closest rational number. in this case, the closest rational number is found to be 1/358 (or 1h/166h). therefore, 0h and 165h should be written to the cfnum and cfden registers respectively. note that the cf frequency is multiplied by the contents of (cfnum + 1) / (cfden + 1). with the cf divide registers contents equal to 1h/166h, the output frequency is given as 2797hz / 358 = 3.905hz. this setting has an error of -0.1%. calibrating cf is made easy by using the calibration mode on the ade7753. the critical part of this approach is that the line frequency needs to be exactly known. if this is not possible, the frequency can be measured by using the pe- riod register of the ade7753. note that changing wgain[11:0] register will also affect the output frequency from cf. the wgain register has a gain adjustment of 0.0244% / lsb. determine the kwhr/lsb calibration coefficient the active energy register (aenergy) can be used to calculate energy. a full description of this register can be found in the energy calculation section. the aenergy reg- ister gives the user both sign and magnitude information regarding energy consumption. on completion of the cf frequency output calibration, i.e., after adjusting the cf frequency divider and the watt gain (wgain) register, the second stage of the calibration is to determine the kwh/lsb coefficient for the aenergy register. equation 26 below shows how laenergy can be used to calculate the calibra- tion coefficient. fl 2 0] : 3 laenergy[2 0] : linecyc[15 seconds/hr 3600 kw) (in power n calibratio kwhr/lsb = (26) once the coefficient is determined, the mcu can compute the energy consumption at any time by reading the aenergy contents and multiplying by the coefficient to calculate kwh. in the above example, at 4.4kw, after 255 half cycles (at 60hz), the resulting laenergy is approximately 2971 decimal. the kwhr/lsb can therefore be calculated to be 8.74 10 -7 kwhr/lsb using the above equation.
ade7753 ?27? rev. prf 10/02 preliminary technical data clkin frequency in this datasheet, the characteristics of the ade7753 is shown with clkin frequency equals 3.579545 mhz. however, the ade7753 is designed to have the same accuracy at any clkin frequency within the specified range. if the clkin frequency is not 3.579545mhz, various timing and filter characteristics will need to be redefined with the new clkin frequency. for example, the cut-off frequencies of all digital filters (lpf1, lpf2, hpf1, etc.) will shift in proportion to the change in clkin frequency according to the following equation: mhz frequency clkin frequency original frequency new 579545 . 3 = (27) the change of clkin frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (sclk). but one needs to observe the read/write timing of the serial data transfer-see ade7753 timing characteristics . table iii lists various timing changes that are affected by clkin fre- quency. table iii frequency dependencies of the ade7753 parameters parameter clkin dependency nyquist frequency for ch 1&2 adcs clkin/8 phcal resolution (seconds per lsb) 4/clkin active energy register update rate (hz) clkin/4 waveform sampling rate (number of samples per second) wavsel 1,0 = 0 0 clkin/128 0 1 clkin/256 1 0 clkin/512 1 1 clkin/1024 maximum zxtout period 524,288/clkin suspending the ade7753 functionality the analog and the digital circuit can be suspended sepa- rately. the analog portion of the ade7753 can be suspended by setting the asuspend bit (bit 4) of the mode register to logic high see mode register . in suspend mode, all waveform samples from the adcs will be set to zeros. the digital circuitry can be halted by stopping the clkin input and maintaining a logic high or low on clkin pin. the ade7753 can be reactivated by restoring the clkin input and setting the asuspend bit to logic low. checksum register the ade7753 has a checksum register (checksum[5:0]) to ensure the data bits received in the last serial read operation are not corrupted. the 6-bit checksum register is reset before the first bit (msb of the register to be read) is put on the dout pin. during a serial read operation, when each data bit becomes available on the rising edge of sclk, the bit will be added to the checksum register. in the end of the serial read operation, the content of the checksum register will equal to the sum of all ones in the register previously read. using the checksum register, the user can determine if an error has occured during the last read operation. note that a read to the checksum register will also generate a checksum of the checksum register itself. checksum register content of register (n-bytes) dout + +  addr: 3eh figure 48? checksum register for serial interface read
ade7753 ?28? rev. prf 10/02 preliminary technical data ade7753 serial interface all ade7753 functionality is accessible via several on-chip registers ? see figure 49. the contents of these registers can be updated or read using the on-chip serial interface. after power-on or toggling the reset pin low or a falling edge on cs , the ade7753 is placed in communications mode. in communications mode the ade7753 expects a write to its communications register. the data written to the communi- cations register determines whether the next data transfer operation will be read or a write and also which register is accessed. therefore all data transfer operations with the ade7753, whether a read or a write, must begin with a write to the communications register. communications register register # 1 register # 2 register # 3 register # n-1 register # n in out register address decode din dout in out in out in out in out figure 49? addressing ade7753 registers via the communications register the communications register is an eight bit wide register. the msb determines whether the next data transfer opera- tion is a read or a write. the 5 lsbs contain the address of the register to be accessed. see ade7753 communications register for a more detailed description. figure 50 and 51 show the data transfer sequences for a read and write operation respectively. on completion of a data transfer (read or write) the ade7753 once again enters communications mode. communications register write cs din dout sclk 0 00 address multibyte read data figure 50? reading data from the ade7753 via the serial interface communications register write cs din sclk 1 00 address multibyte write data figure 51? writing data to the ade7753 via the serial inter- face a data transfer is complete when the lsb of the ade7753 register being addressed (for a write or a read) is transferred to or from the ade7753. the serial interface of the ade7753 is made up of four signals sclk, din, dout and cs . the serial clock for a data transfer is applied at the sclk logic input. this logic input has a schmitt-trigger input structure, which allows slow rising (and falling) clock edges to be used. all data transfer operations are synchronized to the serial clock. data is shifted into the ade7753 at the din logic input on the falling edge of sclk. data is shifted out of the ade7753 at the dout logic output on a rising edge of sclk. the cs logic input is the chip select input. this input is used when multiple devices share the serial bus. a falling edge on cs also resets the serial interface and places the ade7753 in communications mode. the cs input should be driven low for the entire data transfer operation. bringing cs high during a data transfer operation will abort the transfer and place the serial bus in a high impedance state. the cs logic input may be tied low if the ade7753 is the only device on the serial bus. however with cs tied low, all initiated data transfer operations must be fully completed, i.e., the lsb of each register must be transferred as there is no other way of bringing the ade7753 back into communications mode without resetting the entire device, i.e., using reset . ade7753 serial write operation the serial write sequence takes place as follows. with the ade7753 in communications mode (i.e. the cs input logic low), a write to the communications register first takes place. the msb of this byte transfer is a 1, indicating that the data transfer operation is a write. the lsbs of this byte contain the address of the register to be written to. the ade7753 starts shifting in the register data on the next falling edge of sclk. all remaining bits of register data are shifted in on the falling edge of subsequent sclk pulses ? see figure 51. as explained earlier the data write is initiated by a write to the communications register followed by the data. during a data write operation to the ade7753, data is transferred to all on- chip registers one byte at a time. after a byte is transferred into the serial port, there is a finite time before it is transferred to one of the ade7753 on-chip registers. although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register, this second byte transfer should not finish until at least 4s after the end of the previous byte transfer. this functionality is expressed in the timing specification t 6 - see figure 51. if a write operation is aborted during a byte transfer ( cs brought high), then that byte will not be written to the destination register. destination registers may be up to 3 bytes wide ? see ade7753 register descriptions . hence the first byte shifted into the serial port at din is transferred to the msb (most significant byte) of the destination register. if the addressed register is 12 bits wide, for example, a two-byte data transfer must take place. the data is always assumed to be right justified, therefore in this case, the four msbs of the first byte would be ignored and the 4 lsbs of the first byte written to the ade7753 would be the 4msbs of the 12-bit word. figure 52 illustrates this example.
ade7753 ?29? rev. prf 10/02 preliminary technical data figure 52 ? serial interface write timing diagram figure 53?12 bit serial write operation ade7753 serial read operation during a data read operation from the ade7753 data is shifted out at the dout logic output on the rising edge of sclk. as was the case with the data write operation, a data read must be preceded with a write to the communications register. with the ade7753 in communications mode (i.e. cs logic low) an eight bit write to the communications register first takes place. the msb of this byte transfer is a 0, indicating that the next data transfer operation is a read. the lsbs of this byte contain the address of the register which is to be read. the ade7753 starts shifting out of the register data on the next rising edge of sclk ? see figure 54. at this point the dout logic output leaves its high impedance state and starts driving the data bus. all remaining bits of register data are shifted out on subsequent sclk rising edges. the serial interface also enters communications mode again as soon as the read has been completed. at this point the dout logic output enters a high impedance state on the falling edge of the last sclk pulse. the read operation may be aborted by bringing the cs logic input high before the data transfer is complete. the dout output enters a high impedance state on the rising edge of cs . when an ade7753 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. this allows the ade7753 to modify its on-chip registers without the risk of corrupting data during a multi byte transfer. note when a read operation follows a write operation, the read command (i.e., write to communications register) should not happen for at least 4s after the end of the write operation. if the read command is sent within 4s of the write operation, the last byte of the write operation may be lost. the is given as timing specification t 9 . figure 54? serial interface read timing diagram cs sclk din a4 a3 a2 a1 a0 db7 most significant byte t 1 t 2 t 3 t 4 t 5 t 8 1 db0 db7 db0 t 6 least significant byte t 7 t 7 00 command byte sclk xxxx db11 db10 db9 db8 din most significant byte db3 db2 db1 db0 db7 db6 db5 db4 least significant byte cs sclk din a4 a3 a2 a1 a0 t 1 t 11 t 11 t 9 db7 dout t 12 db0 db0 db7 t 10 t 13 most significant byte least significant byte 000 command byte
ade7753 ?30? rev. prf 10/02 preliminary technical data ade7753 register list address name r/w # of bits default description 01h waveform r 24 bits 0h the waveform register is a r ead-only register. this register contains the sampled waveform data from either channel 1, channel 2 or the active power signal. the data source and the length of the waveform registers are selected by data bits 14 and 13 in the mode register - see channel 1 & 2 sampling . 02h aenergy r 24 bits 0h the active energy register. active power is accumulated (integrated) over time in this 24-bit, read-only register. the energy register can hold a minimum of 6 seconds of active energy information with full scale analog inputs before it overflows - see energy calculation . 03h raenergy r 24 bits 0h same as t he active energy register except that the register is reset to zero following a read operation 04h laenergy r 24 bits 0h line accumulation active energy register. the instantaneous active power is accumulated in this read-only register over the lincyc number of half line cycles. 05h vaenergy r 24 bits 0h apparent energy register. apparent power is accumulated over time in this read-only register. 06h rvaenergy r 24 bits 0h same as the vaenergy register except that the register is reset to zero following a read operation. 07h lvaenergy r 24 bits 0h apparent energy register. the instantaneous real power is accumulated in this read-only register over the linecyc number of half line cycles 08h lvarenergy r 24 bits 0h reactive energy register. the instantaneous reactive power is accumulated in this read-only register over the linecyc number of half line cycles. 09h mode r/w 16 bits 000ch the mode register. this is a 16-bit register through which most of the ade7753 functionality is accessed. signal sample rates, filter enabling and calibration modes are selected by writing to this register. the contents may be read at any time?see mode register . 0ah irqen r/w 16 bits 40h interrupt enable register. ade7753 interrupts may be deactivated at any time by setting the corresponding bit in this 8- bit enable register to logic zero. the status register will continue to register an interrupt event even if disabled. however, the irq output will not be activated?see ade7753 interrupts . 0bh status r 16 bits 0h the interrupt status register. this is an 8-bit read-only register. the status register contains information regarding the source of ade7753 interrupts - see ade7753 interrupts . 0ch rststatus r 16 bits 0h same as the interrupt status register except that the register contents are reset to zero (all flags cleared) after a read operation. 0dh ch1os r/w 8 bits 00h channel 1 offset adjust. bit 6 is not used. writing to bits 0 to 5 allows offsets on channel 1 to be removed ? see analog inputs and ch1os register . writing a logic one to the msb of this register enables the digital integrator on channel 1, a zero disables the integrator. the default value of this bit is zero. 0eh ch2os r/w 8 bits 0h channel 2 offset adjust. bit 6 and 7 not used. writing to bits 0 to 5 of this register allows any offsets on channel 2 to be removed - see analog inputs . 0fh gain r/w 8 bits 0h pga gain adjust. this 8-bit register is used to adjust the gain selection for the pga in channel 1 and 2 - see analog inputs .
ade7753 ?31? rev. prf 10/02 preliminary technical data address name r/w # of bits default description 10h phcal r/w 6 bits 0dh phase calibration register. the phase relationship between channel 1 and 2 can be adjusted by writing to this 6-bit register. the valid content of this 2's compliment register is between 1dh to 21h. at line frequency of 60hz, this is a range from -2.06 to +0.7 degrees. ?see phase compensation . 11h apos r/w 16 bits 0h active power offset correction. this 16-bit register allows small offsets in the active power calculation to be removed ? see active power calculation . 12h wgain r/w 12 bits 0h power gain adjust. this is a 12-bit register. the active power calculation can be calibrated by writing to this register. the calibration range is 50% of the nominal full scale active power. the resolution of the gain adjust is 0.0244% / lsb?see channel 1 adc gain adjust . 13h wdiv r/w 8 bits 0h active energy divider register. the internal active energy register is divided by the value of this register before being stored in the aenergy register. 14h cfnum r/w 12 bits 3fh cf frequency divider numerator register. the output frequency on the cf pin is adjusted by writing to this 12-bit read/write register ? see energy to frequency conversion. 15h cfden r/w 12 bits 3fh cf frequency divider denominator register. the output frequency on the cf pin is adjusted by writing to this 12-bit read/write register ? see energy to frequency conversion. 16h irms r 24 bits 0h channel 1 rms value (current channel). 17h vrms r 24 bits 0h channel 2 rms value (voltage channel). 18h irmsos r/w 12 bits 0h channel 1 rms offset correction register 19h vrmsos r/w 12 bits 0h channel 2 rms offset correction register 1ah vagain r/w 12 bits 0h apparent gain register. apparent power calculation can be calibrated by writing this register. the calibration range is 50% of the nominal full scale real power. the resolution of the gain adjust is 0.02444% / lsb. 1bh vadiv r/w 8 bits 0h apparent energy divider register. the internal apparent energy register is divided by the value of this register before being stored in the vaenergy register. 1ch linecyc r/w 15 bits fffh line cycle energy accumulation mode line-cycle register. this 15-bit register is used during line cycle energy accumulation mode to set the number of half line cycles for energy accumulation - see line cycle energy accumulation mode . 1dh zxtout r/w 12 bits fffh zero-cross time out. if no zero crossings are detected on channel 2 within a time period specified by this 12-bit register, the interrupt request line ( irq ) will be activated. the maximum time-out period is 0.15 second - see zero crossing detection . 1eh sagcyc r/w 8 bits f f h sag line cycle register. this 8-bit register specifies the number of consecutive line cycles the signal on channel 2 must be below saglvl before the sag output is activated - see voltage sag detection 1fh saglvl r/w 8 bits 0h sag voltage level. an 8-bit write to this register determines at what peak signal level on channel 2 the sag pin will become active. the signal must remain low for the number of cycles specified in the sagcyc register before the sag pin is activated?see line voltage sag detection . 20h ipklvl r/w 8 bits f f h channel 1 peak level threshold (current channel). this register sets the level of the current peak detection. if the channel 1 input exceeds this level, the pki flag in the status register is set.
ade7753 ?32? rev. prf 10/02 preliminary technical data ade7753 register descriptions all ade7753 functionality is accessed via the on-chip registers. each register is accessed by first writing to the communications register and then transferring the register data. a full description of the serial interface protocol is given i n the serial interface section of this data sheet. communications register the communications register is an 8-bit, write-only register which controls the serial data transfer between the ade7753 and the host processor. all data transfer operations must begin with a write to the communications register. the data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. table iv below outlines the bit designations for the communications register. table v. communications register bit bit description location mnemonic 0 to 5 a0 to a5 the six lsbs of the communications register specify the register for the data transfer operation. table iii lists the address of each ade7753 on-chip register. 6 reserved this bit is unused and should be set to zero. 7w/ r when this bit is a logic one the data transfer operation immediately following the write to the communications register will be interpreted as a write to the ade7753. when this bit is a logic zero the data transfer operation immediately following the write to the communications register will be interpreted as a read operation. db0 w/r a4 a3 a2 a1 a0 0a5 db1 db2 db3 db4 db5 db6 db7 address name r/w # of bits default description 21h vpklvl r/w 8 bits f f h channel 2 peak level threshold (voltage channel). this register sets the level of the voltage peak detection. if the channel 2 input exceeds this level, the pkv flag in the status register is set. 22h ipeak r 24 bits 0h channel 1 peak register. the maximum input value of the current channel since the last read of the register is stored in this register. 23h rstipeak r 24 bits 0h same as channel 1 peak register except that the register contents are reset to 0 after read. 24h vpeak r 24 bits 0h channel 2 peak register. the maximum input value of the voltage channel since the last read of the register is stored in this register. 25h rstvpeak r 24 bits 0h same as channel 2 peak register except that the register contents are reset to 0 after a read. 26h temp r 8 bits 0h temperature register. this is an 8-bit register which contains the result of the latest temperature conversion ? see temperature measurement . 27h period r 15 bits 0h period of the channel 2 (volatge channel) input estimated by zero-crossing processing. 28h- 3ch reserved 3dh tmode r/w 8 bits - test mode register 3eh chksum r 6 bits 0h checksum register. this 6-bit read only register is equal to the sum of all the ones in the previous read ? see ade7753 serial read operation. 3fh dierev r 8 bits - die revision register. this 8-bit read only register contains the revision number of the silicon.
ade7753 ?33? rev. prf 10/02 preliminary technical data mode register (09h) the ade7753 functionality is configured by writing to the mode register. table vi below summarizes the functionality of each bit in the mode register . table vi : mode register bit bit default location mnemonic value description 0 dishpf 0 the hpf (high pass filter) in channel 1 is disabled when this bit is set. 1 dislpf2 0 the lpf (low pass filter) after the multiplier (lpf2) is disabled when this bit is set. 2 discf 1 the frequency output cf is disabled when this bit is set 3 dissag 1 the line voltage sag detection is disabled when this bit is set 4 asuspend 0 by setting this bit to logic one, both ade7753's a/d converters can be turned off. in normal operation, this bit should be left at logic zero. all digital functionality can be stopped by suspending the clock signal at clkin pin. 5 tempsel 0 the temperature conversion starts when this bit is set to one. this bit is automatically reset to zero when the temperature conversion is finished. 6 swrst 0 software chip reset. a data transfer should not take place to the ade7753 for at least 18s after a software reset. 7 cycmode 0 setting this bit to a logic one places the chip in line cycle energy accumulation mode. 8 disch1 0 adc 1 (channel 1) inputs are internally shorted together. 9 disch2 0 adc 2 (channel 2) inputs are internally shorted together. 10 swap 0 by setting this bit to logic 1 the analog inputs v2p and v2n are connected to adc 1 and the analog inputs v1p and v1n are connected to adc 2. 12, 11 dtrt1,0 00 t hese bits are used to select the waveform register update rate dtrt 1 dtrt0 upd ate rate 0 0 27.9ksps (clkin/128) 0 1 14ksps (clkin/256) 1 0 7ksps (clkin/512) 1 1 3.5ksps (clkin/1024) 14, 13 wavsel1,0 00 these bits are used to select the source of the sampled data for the waveform register wavsel1,0 length source 0 0 24 bits active power signal (output of lpf2) 0 1 reserved 1 0 24 bits channel 1 1 1 24 bits channel 2 15 poam 0 writing a logic one to this bit will allow only positive power to be accumulated in the ade7753. the default value of this bit is 0. mode register* addr: 09h 0 1 2 3 4 5 6 7 00 1 1 0 0 0 0 poam (positive only accumulation) wavsel (wave form selection for sample mode) 00 = lpf2 01= reserved 10 = ch1 11 = ch2 dishpf (disable hpf in channel 1) dislpf2 discf (disable frequency output cf) dissag (disable sag output) *register contents show power on defaults (suspend ch1&ch2 adc?s) 8 9 10 11 12 13 14 15 00 0 0 0 0 0 0 dtrt (waveform samples output data rate) 00 = 27.9ksps (clkin/128) 01 = 14.4 ksps (clkin/256) 10 = 7.2 ksps (clkin/512) 11 = 3.6 ksps (clkin/1024) swap (swap ch1 & ch2 adcs) disch2 (short the analog inputs on channel 2) disch1 (short the analog inputs on channel 1) swrst (software chip reset) cycmode (line cycle energy accumulation mode) (disable lpf2 after multiplier) stemp asuspend (start temperature sensing)
ade7753 ?34? rev. prf 10/02 preliminary technical data interrupt status register (0bh) / reset interrupt status register (0ch) /interrupt enable register (0ah) the status register is used by the mcu to determine the source of an interrupt request ( irq ). when an interrupt event occurs in the ade7753, the corresponding flag in the interrupt status register is set logic high. if the enable bit for this flag is l ogic one in the interrupt enable register, the irq logic output goes active low. when the mcu services the interrupt it must first carry out a read from the interrupt status register to determine the source of the interrupt. table vii: interrupt status register, reset interrupt status register & interrupt enable register bit interrupt location flag description 0h aehf indicates that an interrupt was caused by the 0 to 1 transition of the msb of the active energy register (i.e. the aenergy register is half full) 1h s a g indicates that an interrupt was caused by a sag on the line voltage or no zero crossings were detected. 2h cycend indicates the end of energy accumulation over an integer number of half line cycles as defined by the content of the linecyc register?see line cycle energy accumulation mode 3h wsmp indicates that new data is present in the waveform register. 4h z x this status bit reflects the status of the zx logic ouput?see zero crossing detection 5h temp indicates that a temperature conversion result is available in the temperature register. 6h reset indicates the end of a reset (for both software or hardware reset). the corresponding enable bit has no function in the interrupt enable register, i.e. this status bit is set at the end of a reset, but it cannot be enabled to cause an interrupt. 7h aeof indicates that the active energy register has overflowed. 8h pkv indicates that waveform sample from channel2 has exceeded the vpklvl value. 9h pki indicates that waveform sample from channel1 has exceeded the ipklvl value. ah vaehf indicates that an interrupt was caused by the 0 to 1 transition of the msb of the apparent energy register (i.e. the vaenergy register is half full) bh vaeof indicates that the apparent enrgy register has overflowed. ch zxto indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number of line cycles?see zero crossing time out dh ppos indicates that the power has gone from negative to positive. eh pneg indicates that the power has gone from positive to negative. fh reserved reserved
ade7753 ?35? rev. prf 10/02 preliminary technical data outline dimensions dimensions shown in inches and (mm) 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 20-shrink small outline package (rs-20)
ade7753 ?36? rev. prf 10/02 preliminary technical data ade7753 errata (rev 1.0) the following is a list of known issues with the first revision of the ade7753 silicon (rev 1.0). these issues will be resolved in the next version. samples of this version of the silicon can be identified from the content of the dierev regsiter (address 3fh). the content of dierev register is 2 for rev 1.2 silicon. in addition, the branding on top of the package for rev 1.2 should be as shown below: 20 11 10 1 ad7753 xrs 0240 k58207 errata 1. sagcyc the contents of sagcyc register is equivalent to (sagcyc-1). for example, if the desired number of linecycles for sag detection is 20d line cycles, one should write 21d to the sagcyc register. this is not a silicon bug. 2. cfnum and cfden cfnum should always be less than cfden. the behav- ior of the output frequency is not guaranteed for cf. this is not a silicon bug.
ade7753 ?37? rev. prf 10/02 preliminary technical data revision history the main reason for revising the datasheet from version pr.d to pr.f is to correct some of the mistakes contained in the pr.d and pr.e version. in addition, changes were made to the silicon to fix bugs noted in the errata list and to modify the product definition. the list below highlights the important changes from pr.d to pr.f. note that all page numbers are referring to that of pr.f. page 4 read timing t 9 is determined to be 3.1us. page 12 the sagcyc register value represents full-line cycles and not half-line cycles. the line voltage sag detection section text was changed to reflect this design update. figure 13 shows 3 line cycles, 3h in the sagcyc register, changed from 6 half line cycles, 6h in the sagcyc register. the section explaining figure 13 has also changed accordingly. page 13 peak level record section was changed to show that the quantity stored in vpeak register is 2 times the absolute value of the waveform register contents for ch2. ipeak is 1 times the absolute value of the ch1 waveform. page 18 1. the phase calibration register resolution has changed to 0.048 from 0.024. this section calculations have been changed to reflect this new resolution. 2. figure 27 updated with new phcal range and delay block rate. page 20 figure 36 timing was updated. page 21 1. the internal active energy accumulation register is 47 bits instead of 53 bits. the equation also shows this change. this change is also implemented in the equations of page 25 as well as figures 45 and 47 on page 25. 2. the maximum output frequency is changed to 23hz. 3. text added to explain cfnum must be less than cfden. page 22 1. figure 39 shows the actual internal register length to be 47 bits. this change is also on page 23, figure 41. 2. line cycle energy accumulation mode section changed to 15 bits for linecyc register. page 26 1. equation 25 changed to have 2^27 bits for the denomina- tor. 2. content of laenergy register is 2971.4, and the cf frequency output in the example calculation is 1398.3 hz. 3. the calculation of cfnum and cfden changed according to the effect of the abovementioned changes. page 31 1. the definition of the sagcyc a register has changed to full line cycles. linecyc corrected to say 15 bits and remains half line cycles. 2. the phcal register description changed to reflect the new effective length and resolution of the register and default value of 0d.


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